Loading drivers/regulator/qpnp-labibb-regulator.c +44 −10 Original line number Diff line number Diff line Loading @@ -65,6 +65,7 @@ #define REG_LAB_PRECHARGE_CTL 0x5E #define REG_LAB_SOFT_START_CTL 0x5F #define REG_LAB_SPARE_CTL 0x60 #define REG_LAB_MISC_CTL 0x60 /* PMI8998/PM660A */ #define REG_LAB_PFM_CTL 0x62 /* LAB registers for PM660A */ Loading Loading @@ -137,6 +138,9 @@ #define LAB_SPARE_TOUCH_WAKE_BIT BIT(3) #define LAB_SPARE_DISABLE_SCP_BIT BIT(0) /* REG_LAB_MISC_CTL */ #define LAB_AUTO_GM_BIT BIT(4) /* REG_LAB_PFM_CTL */ #define LAB_PFM_EN_BIT BIT(7) Loading Loading @@ -1854,7 +1858,7 @@ static int qpnp_labibb_save_settings(struct qpnp_labibb *labibb) static int qpnp_labibb_ttw_enter_ibb_common(struct qpnp_labibb *labibb) { int rc = 0; u8 val; u8 val, mask; val = 0; rc = qpnp_labibb_write(labibb, labibb->ibb_base + REG_IBB_PD_CTL, Loading @@ -1874,10 +1878,16 @@ static int qpnp_labibb_ttw_enter_ibb_common(struct qpnp_labibb *labibb) return rc; } if (labibb->pmic_rev_id->pmic_subtype == PMI8998_SUBTYPE) { val = 0; mask = IBB_DIS_DLY_MASK; } else { val = IBB_WAIT_MBG_OK; mask = IBB_DIS_DLY_MASK | IBB_WAIT_MBG_OK; } rc = qpnp_labibb_sec_masked_write(labibb, labibb->ibb_base, REG_IBB_PWRUP_PWRDN_CTL_2, IBB_DIS_DLY_MASK | IBB_WAIT_MBG_OK, val); REG_IBB_PWRUP_PWRDN_CTL_2, mask, val); if (rc < 0) { pr_err("write to register %x failed rc = %d\n", REG_IBB_PWRUP_PWRDN_CTL_2, rc); Loading Loading @@ -1953,7 +1963,7 @@ static int qpnp_labibb_ttw_enter_ibb_pmi8950(struct qpnp_labibb *labibb) static int qpnp_labibb_regulator_ttw_mode_enter(struct qpnp_labibb *labibb) { int rc = 0; u8 val; u8 val, reg; /* Save the IBB settings before they get modified for TTW mode */ if (!labibb->ibb_settings_saved) { Loading Loading @@ -2015,10 +2025,17 @@ static int qpnp_labibb_regulator_ttw_mode_enter(struct qpnp_labibb *labibb) } val = LAB_SPARE_DISABLE_SCP_BIT; if (labibb->pmic_rev_id->pmic_subtype != PMI8950_SUBTYPE) val |= LAB_SPARE_TOUCH_WAKE_BIT; rc = qpnp_labibb_write(labibb, labibb->lab_base + REG_LAB_SPARE_CTL, &val, 1); if (labibb->pmic_rev_id->pmic_subtype == PMI8998_SUBTYPE) { reg = REG_LAB_MISC_CTL; val |= LAB_AUTO_GM_BIT; } else { reg = REG_LAB_SPARE_CTL; } rc = qpnp_labibb_write(labibb, labibb->lab_base + reg, &val, 1); if (rc < 0) { pr_err("qpnp_labibb_write register %x failed rc = %d\n", REG_LAB_SPARE_CTL, rc); Loading Loading @@ -2048,7 +2065,15 @@ static int qpnp_labibb_regulator_ttw_mode_enter(struct qpnp_labibb *labibb) case PMI8950_SUBTYPE: rc = qpnp_labibb_ttw_enter_ibb_pmi8950(labibb); break; case PMI8998_SUBTYPE: rc = labibb->lab_ver_ops->ps_ctl(labibb, 70, true); if (rc < 0) break; rc = qpnp_ibb_ps_config(labibb, true); break; } if (rc < 0) { pr_err("Failed to configure TTW-enter for IBB rc=%d\n", rc); return rc; Loading Loading @@ -2081,7 +2106,7 @@ static int qpnp_labibb_ttw_exit_ibb_common(struct qpnp_labibb *labibb) static int qpnp_labibb_regulator_ttw_mode_exit(struct qpnp_labibb *labibb) { int rc = 0; u8 val; u8 val, reg; if (!labibb->ibb_settings_saved) { pr_err("IBB settings are not saved!\n"); Loading Loading @@ -2115,8 +2140,14 @@ static int qpnp_labibb_regulator_ttw_mode_exit(struct qpnp_labibb *labibb) } val = 0; rc = qpnp_labibb_write(labibb, labibb->lab_base + REG_LAB_SPARE_CTL, &val, 1); if (labibb->pmic_rev_id->pmic_subtype == PMI8998_SUBTYPE) { reg = REG_LAB_MISC_CTL; val |= LAB_AUTO_GM_BIT; } else { reg = REG_LAB_SPARE_CTL; } rc = qpnp_labibb_write(labibb, labibb->lab_base + reg, &val, 1); if (rc < 0) { pr_err("qpnp_labibb_write register %x failed rc = %d\n", REG_LAB_SPARE_CTL, rc); Loading Loading @@ -3692,6 +3723,9 @@ static int qpnp_labibb_check_ttw_supported(struct qpnp_labibb *labibb) case PMI8950_SUBTYPE: /* TTW supported for all revisions */ break; case PMI8998_SUBTYPE: /* TTW supported for all revisions */ break; default: pr_info("TTW mode not supported for PMIC-subtype = %d\n", labibb->pmic_rev_id->pmic_subtype); Loading Loading
drivers/regulator/qpnp-labibb-regulator.c +44 −10 Original line number Diff line number Diff line Loading @@ -65,6 +65,7 @@ #define REG_LAB_PRECHARGE_CTL 0x5E #define REG_LAB_SOFT_START_CTL 0x5F #define REG_LAB_SPARE_CTL 0x60 #define REG_LAB_MISC_CTL 0x60 /* PMI8998/PM660A */ #define REG_LAB_PFM_CTL 0x62 /* LAB registers for PM660A */ Loading Loading @@ -137,6 +138,9 @@ #define LAB_SPARE_TOUCH_WAKE_BIT BIT(3) #define LAB_SPARE_DISABLE_SCP_BIT BIT(0) /* REG_LAB_MISC_CTL */ #define LAB_AUTO_GM_BIT BIT(4) /* REG_LAB_PFM_CTL */ #define LAB_PFM_EN_BIT BIT(7) Loading Loading @@ -1854,7 +1858,7 @@ static int qpnp_labibb_save_settings(struct qpnp_labibb *labibb) static int qpnp_labibb_ttw_enter_ibb_common(struct qpnp_labibb *labibb) { int rc = 0; u8 val; u8 val, mask; val = 0; rc = qpnp_labibb_write(labibb, labibb->ibb_base + REG_IBB_PD_CTL, Loading @@ -1874,10 +1878,16 @@ static int qpnp_labibb_ttw_enter_ibb_common(struct qpnp_labibb *labibb) return rc; } if (labibb->pmic_rev_id->pmic_subtype == PMI8998_SUBTYPE) { val = 0; mask = IBB_DIS_DLY_MASK; } else { val = IBB_WAIT_MBG_OK; mask = IBB_DIS_DLY_MASK | IBB_WAIT_MBG_OK; } rc = qpnp_labibb_sec_masked_write(labibb, labibb->ibb_base, REG_IBB_PWRUP_PWRDN_CTL_2, IBB_DIS_DLY_MASK | IBB_WAIT_MBG_OK, val); REG_IBB_PWRUP_PWRDN_CTL_2, mask, val); if (rc < 0) { pr_err("write to register %x failed rc = %d\n", REG_IBB_PWRUP_PWRDN_CTL_2, rc); Loading Loading @@ -1953,7 +1963,7 @@ static int qpnp_labibb_ttw_enter_ibb_pmi8950(struct qpnp_labibb *labibb) static int qpnp_labibb_regulator_ttw_mode_enter(struct qpnp_labibb *labibb) { int rc = 0; u8 val; u8 val, reg; /* Save the IBB settings before they get modified for TTW mode */ if (!labibb->ibb_settings_saved) { Loading Loading @@ -2015,10 +2025,17 @@ static int qpnp_labibb_regulator_ttw_mode_enter(struct qpnp_labibb *labibb) } val = LAB_SPARE_DISABLE_SCP_BIT; if (labibb->pmic_rev_id->pmic_subtype != PMI8950_SUBTYPE) val |= LAB_SPARE_TOUCH_WAKE_BIT; rc = qpnp_labibb_write(labibb, labibb->lab_base + REG_LAB_SPARE_CTL, &val, 1); if (labibb->pmic_rev_id->pmic_subtype == PMI8998_SUBTYPE) { reg = REG_LAB_MISC_CTL; val |= LAB_AUTO_GM_BIT; } else { reg = REG_LAB_SPARE_CTL; } rc = qpnp_labibb_write(labibb, labibb->lab_base + reg, &val, 1); if (rc < 0) { pr_err("qpnp_labibb_write register %x failed rc = %d\n", REG_LAB_SPARE_CTL, rc); Loading Loading @@ -2048,7 +2065,15 @@ static int qpnp_labibb_regulator_ttw_mode_enter(struct qpnp_labibb *labibb) case PMI8950_SUBTYPE: rc = qpnp_labibb_ttw_enter_ibb_pmi8950(labibb); break; case PMI8998_SUBTYPE: rc = labibb->lab_ver_ops->ps_ctl(labibb, 70, true); if (rc < 0) break; rc = qpnp_ibb_ps_config(labibb, true); break; } if (rc < 0) { pr_err("Failed to configure TTW-enter for IBB rc=%d\n", rc); return rc; Loading Loading @@ -2081,7 +2106,7 @@ static int qpnp_labibb_ttw_exit_ibb_common(struct qpnp_labibb *labibb) static int qpnp_labibb_regulator_ttw_mode_exit(struct qpnp_labibb *labibb) { int rc = 0; u8 val; u8 val, reg; if (!labibb->ibb_settings_saved) { pr_err("IBB settings are not saved!\n"); Loading Loading @@ -2115,8 +2140,14 @@ static int qpnp_labibb_regulator_ttw_mode_exit(struct qpnp_labibb *labibb) } val = 0; rc = qpnp_labibb_write(labibb, labibb->lab_base + REG_LAB_SPARE_CTL, &val, 1); if (labibb->pmic_rev_id->pmic_subtype == PMI8998_SUBTYPE) { reg = REG_LAB_MISC_CTL; val |= LAB_AUTO_GM_BIT; } else { reg = REG_LAB_SPARE_CTL; } rc = qpnp_labibb_write(labibb, labibb->lab_base + reg, &val, 1); if (rc < 0) { pr_err("qpnp_labibb_write register %x failed rc = %d\n", REG_LAB_SPARE_CTL, rc); Loading Loading @@ -3692,6 +3723,9 @@ static int qpnp_labibb_check_ttw_supported(struct qpnp_labibb *labibb) case PMI8950_SUBTYPE: /* TTW supported for all revisions */ break; case PMI8998_SUBTYPE: /* TTW supported for all revisions */ break; default: pr_info("TTW mode not supported for PMIC-subtype = %d\n", labibb->pmic_rev_id->pmic_subtype); Loading