Loading Makefile +1 −1 Original line number Diff line number Diff line VERSION = 4 PATCHLEVEL = 9 SUBLEVEL = 22 SUBLEVEL = 23 EXTRAVERSION = NAME = Roaring Lionus Loading arch/mips/Kconfig +1 −0 Original line number Diff line number Diff line Loading @@ -9,6 +9,7 @@ config MIPS select HAVE_CONTEXT_TRACKING select HAVE_GENERIC_DMA_COHERENT select HAVE_IDE select HAVE_IRQ_EXIT_ON_IRQ_STACK select HAVE_OPROFILE select HAVE_PERF_EVENTS select PERF_USE_VMALLOC Loading arch/mips/include/asm/irq.h +12 −0 Original line number Diff line number Diff line Loading @@ -17,6 +17,18 @@ #include <irq.h> #define IRQ_STACK_SIZE THREAD_SIZE extern void *irq_stack[NR_CPUS]; static inline bool on_irq_stack(int cpu, unsigned long sp) { unsigned long low = (unsigned long)irq_stack[cpu]; unsigned long high = low + IRQ_STACK_SIZE; return (low <= sp && sp <= high); } #ifdef CONFIG_I8259 static inline int irq_canonicalize(int irq) { Loading arch/mips/include/asm/stackframe.h +7 −0 Original line number Diff line number Diff line Loading @@ -216,12 +216,19 @@ LONG_S $25, PT_R25(sp) LONG_S $28, PT_R28(sp) LONG_S $31, PT_R31(sp) /* Set thread_info if we're coming from user mode */ mfc0 k0, CP0_STATUS sll k0, 3 /* extract cu0 bit */ bltz k0, 9f ori $28, sp, _THREAD_MASK xori $28, _THREAD_MASK #ifdef CONFIG_CPU_CAVIUM_OCTEON .set mips64 pref 0, 0($28) /* Prefetch the current pointer */ #endif 9: .set pop .endm Loading arch/mips/kernel/asm-offsets.c +1 −0 Original line number Diff line number Diff line Loading @@ -102,6 +102,7 @@ void output_thread_info_defines(void) OFFSET(TI_REGS, thread_info, regs); DEFINE(_THREAD_SIZE, THREAD_SIZE); DEFINE(_THREAD_MASK, THREAD_MASK); DEFINE(_IRQ_STACK_SIZE, IRQ_STACK_SIZE); BLANK(); } Loading Loading
Makefile +1 −1 Original line number Diff line number Diff line VERSION = 4 PATCHLEVEL = 9 SUBLEVEL = 22 SUBLEVEL = 23 EXTRAVERSION = NAME = Roaring Lionus Loading
arch/mips/Kconfig +1 −0 Original line number Diff line number Diff line Loading @@ -9,6 +9,7 @@ config MIPS select HAVE_CONTEXT_TRACKING select HAVE_GENERIC_DMA_COHERENT select HAVE_IDE select HAVE_IRQ_EXIT_ON_IRQ_STACK select HAVE_OPROFILE select HAVE_PERF_EVENTS select PERF_USE_VMALLOC Loading
arch/mips/include/asm/irq.h +12 −0 Original line number Diff line number Diff line Loading @@ -17,6 +17,18 @@ #include <irq.h> #define IRQ_STACK_SIZE THREAD_SIZE extern void *irq_stack[NR_CPUS]; static inline bool on_irq_stack(int cpu, unsigned long sp) { unsigned long low = (unsigned long)irq_stack[cpu]; unsigned long high = low + IRQ_STACK_SIZE; return (low <= sp && sp <= high); } #ifdef CONFIG_I8259 static inline int irq_canonicalize(int irq) { Loading
arch/mips/include/asm/stackframe.h +7 −0 Original line number Diff line number Diff line Loading @@ -216,12 +216,19 @@ LONG_S $25, PT_R25(sp) LONG_S $28, PT_R28(sp) LONG_S $31, PT_R31(sp) /* Set thread_info if we're coming from user mode */ mfc0 k0, CP0_STATUS sll k0, 3 /* extract cu0 bit */ bltz k0, 9f ori $28, sp, _THREAD_MASK xori $28, _THREAD_MASK #ifdef CONFIG_CPU_CAVIUM_OCTEON .set mips64 pref 0, 0($28) /* Prefetch the current pointer */ #endif 9: .set pop .endm Loading
arch/mips/kernel/asm-offsets.c +1 −0 Original line number Diff line number Diff line Loading @@ -102,6 +102,7 @@ void output_thread_info_defines(void) OFFSET(TI_REGS, thread_info, regs); DEFINE(_THREAD_SIZE, THREAD_SIZE); DEFINE(_THREAD_MASK, THREAD_MASK); DEFINE(_IRQ_STACK_SIZE, IRQ_STACK_SIZE); BLANK(); } Loading