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Commit 914ebf0b authored by Magnus Damm's avatar Magnus Damm Committed by Paul Mundt
Browse files

sh: get rid of div4 clock name 



Remove the name parameter from SH_CLK_DIV4() and
adjust the processor specific code. The lookup
happens using clkdev so the name is unused.

Signed-off-by: default avatarMagnus Damm <damm@opensource.se>
Signed-off-by: default avatarPaul Mundt <lethal@linux-sh.org>
parent 1fe3d198

arch/sh/include/asm/clock.h

+7 −8
Original line number Diff line number Diff line
@@ -126,9 +126,8 @@ int clk_rate_table_find(struct clk *clk, 


int sh_clk_mstp32_register(struct clk *clks, int nr);



#define SH_CLK_DIV4(_name, _parent, _reg, _shift, _div_bitmap, _flags)	\

#define SH_CLK_DIV4(_parent, _reg, _shift, _div_bitmap, _flags)	\

{								\

	.name = _name,							\

	.parent = _parent,					\

	.enable_reg = (void __iomem *)_reg,			\

	.enable_bit = _shift,					\

arch/sh/kernel/cpu/sh4a/clock-sh7343.c

+10 −10
Original line number Diff line number Diff line
@@ -122,18 +122,18 @@ static struct clk_div4_table div4_table = { 
enum { DIV4_I, DIV4_U, DIV4_SH, DIV4_B, DIV4_B3, DIV4_P,

       DIV4_SIUA, DIV4_SIUB, DIV4_NR };



#define DIV4(_str, _reg, _bit, _mask, _flags) \

  SH_CLK_DIV4(_str, &pll_clk, _reg, _bit, _mask, _flags)

#define DIV4(_reg, _bit, _mask, _flags) \

  SH_CLK_DIV4(&pll_clk, _reg, _bit, _mask, _flags)



struct clk div4_clks[DIV4_NR] = {

	[DIV4_I] = DIV4("cpu_clk", FRQCR, 20, 0x1fff, CLK_ENABLE_ON_INIT),

	[DIV4_U] = DIV4("umem_clk", FRQCR, 16, 0x1fff, CLK_ENABLE_ON_INIT),

	[DIV4_SH] = DIV4("shyway_clk", FRQCR, 12, 0x1fff, CLK_ENABLE_ON_INIT),

	[DIV4_B] = DIV4("bus_clk", FRQCR, 8, 0x1fff, CLK_ENABLE_ON_INIT),

	[DIV4_B3] = DIV4("b3_clk", FRQCR, 4, 0x1fff, CLK_ENABLE_ON_INIT),

	[DIV4_P] = DIV4("peripheral_clk", FRQCR, 0, 0x1fff, 0),

	[DIV4_SIUA] = DIV4("siua_clk", SCLKACR, 0, 0x1fff, 0),

	[DIV4_SIUB] = DIV4("siub_clk", SCLKBCR, 0, 0x1fff, 0),

	[DIV4_I] = DIV4(FRQCR, 20, 0x1fff, CLK_ENABLE_ON_INIT),

	[DIV4_U] = DIV4(FRQCR, 16, 0x1fff, CLK_ENABLE_ON_INIT),

	[DIV4_SH] = DIV4(FRQCR, 12, 0x1fff, CLK_ENABLE_ON_INIT),

	[DIV4_B] = DIV4(FRQCR, 8, 0x1fff, CLK_ENABLE_ON_INIT),

	[DIV4_B3] = DIV4(FRQCR, 4, 0x1fff, CLK_ENABLE_ON_INIT),

	[DIV4_P] = DIV4(FRQCR, 0, 0x1fff, 0),

	[DIV4_SIUA] = DIV4(SCLKACR, 0, 0x1fff, 0),

	[DIV4_SIUB] = DIV4(SCLKBCR, 0, 0x1fff, 0),

};



enum { DIV6_V, DIV6_NR };

arch/sh/kernel/cpu/sh4a/clock-sh7366.c

+10 −10
Original line number Diff line number Diff line
@@ -125,18 +125,18 @@ static struct clk_div4_table div4_table = { 
enum { DIV4_I, DIV4_U, DIV4_SH, DIV4_B, DIV4_B3, DIV4_P,

       DIV4_SIUA, DIV4_SIUB, DIV4_NR };



#define DIV4(_str, _reg, _bit, _mask, _flags) \

  SH_CLK_DIV4(_str, &pll_clk, _reg, _bit, _mask, _flags)

#define DIV4(_reg, _bit, _mask, _flags) \

  SH_CLK_DIV4(&pll_clk, _reg, _bit, _mask, _flags)



struct clk div4_clks[DIV4_NR] = {

	[DIV4_I] = DIV4("cpu_clk", FRQCR, 20, 0x1fef, CLK_ENABLE_ON_INIT),

	[DIV4_U] = DIV4("umem_clk", FRQCR, 16, 0x1fff, CLK_ENABLE_ON_INIT),

	[DIV4_SH] = DIV4("shyway_clk", FRQCR, 12, 0x1fff, CLK_ENABLE_ON_INIT),

	[DIV4_B] = DIV4("bus_clk", FRQCR, 8, 0x1fff, CLK_ENABLE_ON_INIT),

	[DIV4_B3] = DIV4("b3_clk", FRQCR, 4, 0x1fff, CLK_ENABLE_ON_INIT),

	[DIV4_P] = DIV4("peripheral_clk", FRQCR, 0, 0x1fff, 0),

	[DIV4_SIUA] = DIV4("siua_clk", SCLKACR, 0, 0x1fff, 0),

	[DIV4_SIUB] = DIV4("siub_clk", SCLKBCR, 0, 0x1fff, 0),

	[DIV4_I] = DIV4(FRQCR, 20, 0x1fef, CLK_ENABLE_ON_INIT),

	[DIV4_U] = DIV4(FRQCR, 16, 0x1fff, CLK_ENABLE_ON_INIT),

	[DIV4_SH] = DIV4(FRQCR, 12, 0x1fff, CLK_ENABLE_ON_INIT),

	[DIV4_B] = DIV4(FRQCR, 8, 0x1fff, CLK_ENABLE_ON_INIT),

	[DIV4_B3] = DIV4(FRQCR, 4, 0x1fff, CLK_ENABLE_ON_INIT),

	[DIV4_P] = DIV4(FRQCR, 0, 0x1fff, 0),

	[DIV4_SIUA] = DIV4(SCLKACR, 0, 0x1fff, 0),

	[DIV4_SIUB] = DIV4(SCLKBCR, 0, 0x1fff, 0),

};



enum { DIV6_V, DIV6_NR };

arch/sh/kernel/cpu/sh4a/clock-sh7722.c

+11 −11
Original line number Diff line number Diff line
@@ -122,31 +122,31 @@ static struct clk_div4_table div4_table = { 
	.div_mult_table = &div4_div_mult_table,

};



#define DIV4(_str, _reg, _bit, _mask, _flags) \

  SH_CLK_DIV4(_str, &pll_clk, _reg, _bit, _mask, _flags)

#define DIV4(_reg, _bit, _mask, _flags) \

  SH_CLK_DIV4(&pll_clk, _reg, _bit, _mask, _flags)



enum { DIV4_I, DIV4_U, DIV4_SH, DIV4_B, DIV4_B3, DIV4_P, DIV4_NR };



struct clk div4_clks[DIV4_NR] = {

	[DIV4_I] = DIV4("cpu_clk", FRQCR, 20, 0x1fef, CLK_ENABLE_ON_INIT),

	[DIV4_U] = DIV4("umem_clk", FRQCR, 16, 0x1fff, CLK_ENABLE_ON_INIT),

	[DIV4_SH] = DIV4("shyway_clk", FRQCR, 12, 0x1fff, CLK_ENABLE_ON_INIT),

	[DIV4_B] = DIV4("bus_clk", FRQCR, 8, 0x1fff, CLK_ENABLE_ON_INIT),

	[DIV4_B3] = DIV4("b3_clk", FRQCR, 4, 0x1fff, CLK_ENABLE_ON_INIT),

	[DIV4_P] = DIV4("peripheral_clk", FRQCR, 0, 0x1fff, 0),

	[DIV4_I] = DIV4(FRQCR, 20, 0x1fef, CLK_ENABLE_ON_INIT),

	[DIV4_U] = DIV4(FRQCR, 16, 0x1fff, CLK_ENABLE_ON_INIT),

	[DIV4_SH] = DIV4(FRQCR, 12, 0x1fff, CLK_ENABLE_ON_INIT),

	[DIV4_B] = DIV4(FRQCR, 8, 0x1fff, CLK_ENABLE_ON_INIT),

	[DIV4_B3] = DIV4(FRQCR, 4, 0x1fff, CLK_ENABLE_ON_INIT),

	[DIV4_P] = DIV4(FRQCR, 0, 0x1fff, 0),

};



enum { DIV4_IRDA, DIV4_ENABLE_NR };



struct clk div4_enable_clks[DIV4_ENABLE_NR] = {

	[DIV4_IRDA] = DIV4("irda_clk", IRDACLKCR, 0, 0x1fff, 0),

	[DIV4_IRDA] = DIV4(IRDACLKCR, 0, 0x1fff, 0),

};



enum { DIV4_SIUA, DIV4_SIUB, DIV4_REPARENT_NR };



struct clk div4_reparent_clks[DIV4_REPARENT_NR] = {

	[DIV4_SIUA] = DIV4("siua_clk", SCLKACR, 0, 0x1fff, 0),

	[DIV4_SIUB] = DIV4("siub_clk", SCLKBCR, 0, 0x1fff, 0),

	[DIV4_SIUA] = DIV4(SCLKACR, 0, 0x1fff, 0),

	[DIV4_SIUB] = DIV4(SCLKBCR, 0, 0x1fff, 0),

};



enum { DIV6_V, DIV6_NR };

arch/sh/kernel/cpu/sh4a/clock-sh7723.c

+11 −11
Original line number Diff line number Diff line
@@ -125,29 +125,29 @@ static struct clk_div4_table div4_table = { 


enum { DIV4_I, DIV4_U, DIV4_SH, DIV4_B, DIV4_B3, DIV4_P, DIV4_NR };



#define DIV4(_str, _reg, _bit, _mask, _flags) \

  SH_CLK_DIV4(_str, &pll_clk, _reg, _bit, _mask, _flags)

#define DIV4(_reg, _bit, _mask, _flags) \

  SH_CLK_DIV4(&pll_clk, _reg, _bit, _mask, _flags)



struct clk div4_clks[DIV4_NR] = {

	[DIV4_I] = DIV4("cpu_clk", FRQCR, 20, 0x0dbf, CLK_ENABLE_ON_INIT),

	[DIV4_U] = DIV4("umem_clk", FRQCR, 16, 0x0dbf, CLK_ENABLE_ON_INIT),

	[DIV4_SH] = DIV4("shyway_clk", FRQCR, 12, 0x0dbf, CLK_ENABLE_ON_INIT),

	[DIV4_B] = DIV4("bus_clk", FRQCR, 8, 0x0dbf, CLK_ENABLE_ON_INIT),

	[DIV4_B3] = DIV4("b3_clk", FRQCR, 4, 0x0db4, CLK_ENABLE_ON_INIT),

	[DIV4_P] = DIV4("peripheral_clk", FRQCR, 0, 0x0dbf, 0),

	[DIV4_I] = DIV4(FRQCR, 20, 0x0dbf, CLK_ENABLE_ON_INIT),

	[DIV4_U] = DIV4(FRQCR, 16, 0x0dbf, CLK_ENABLE_ON_INIT),

	[DIV4_SH] = DIV4(FRQCR, 12, 0x0dbf, CLK_ENABLE_ON_INIT),

	[DIV4_B] = DIV4(FRQCR, 8, 0x0dbf, CLK_ENABLE_ON_INIT),

	[DIV4_B3] = DIV4(FRQCR, 4, 0x0db4, CLK_ENABLE_ON_INIT),

	[DIV4_P] = DIV4(FRQCR, 0, 0x0dbf, 0),

};



enum { DIV4_IRDA, DIV4_ENABLE_NR };



struct clk div4_enable_clks[DIV4_ENABLE_NR] = {

	[DIV4_IRDA] = DIV4("irda_clk", IRDACLKCR, 0, 0x0dbf, 0),

	[DIV4_IRDA] = DIV4(IRDACLKCR, 0, 0x0dbf, 0),

};



enum { DIV4_SIUA, DIV4_SIUB, DIV4_REPARENT_NR };



struct clk div4_reparent_clks[DIV4_REPARENT_NR] = {

	[DIV4_SIUA] = DIV4("siua_clk", SCLKACR, 0, 0x0dbf, 0),

	[DIV4_SIUB] = DIV4("siub_clk", SCLKBCR, 0, 0x0dbf, 0),

	[DIV4_SIUA] = DIV4(SCLKACR, 0, 0x0dbf, 0),

	[DIV4_SIUB] = DIV4(SCLKBCR, 0, 0x0dbf, 0),

};

enum { DIV6_V, DIV6_NR };