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Commit 9146cbd5 authored by Brian Norris's avatar Brian Norris
Browse files

mtd: jz4780_nand: replace if/else blocks with switch/case 



Using switch/case helps make this logic more clear and more robust. With
this structure:

 * it's clear that this driver only support ECC_{HW,SOFT,SOFT_BCH}; and

 * we can sanely handle new ECC unsupported modes (right now, this code
   makes incorrect assumptions about the possible values in the
   nand_ecc_modes_t enum; e.g., what happens with NAND_ECC_HW_OOB_FIRST?)

Signed-off-by: default avatarBrian Norris <computersforpeace@gmail.com>
Cc: Alex Smith <alex@alex-smith.me.uk>
Reviewed-by: default avatarBoris Brezillon <boris.brezillon@free-electrons.com>
Tested-by: default avatarHarvey Hunt <harvey.hunt@imgtec.com>
Acked-by: default avatarHarvey Hunt <harvey.hunt@imgtec.com>
parent 6c1207b5

drivers/mtd/nand/jz4780_nand.c

+19 −15
Original line number Diff line number Diff line
@@ -171,29 +171,33 @@ static int jz4780_nand_init_ecc(struct jz4780_nand_chip *nand, struct device *de 
	chip->ecc.bytes = fls((1 + 8) * chip->ecc.size)	*

				(chip->ecc.strength / 8);



	if (nfc->bch && chip->ecc.mode == NAND_ECC_HW) {

		chip->ecc.hwctl = jz4780_nand_ecc_hwctl;

		chip->ecc.calculate = jz4780_nand_ecc_calculate;

		chip->ecc.correct = jz4780_nand_ecc_correct;

	} else if (!nfc->bch && chip->ecc.mode == NAND_ECC_HW) {

	switch (chip->ecc.mode) {

	case NAND_ECC_HW:

		if (!nfc->bch) {

			dev_err(dev, "HW BCH selected, but BCH controller not found\n");

			return -ENODEV;

		}



	if (chip->ecc.mode == NAND_ECC_HW_SYNDROME) {

		dev_err(dev, "ECC HW syndrome not supported\n");

		return -EINVAL;

	}



	if (chip->ecc.mode != NAND_ECC_NONE)

		chip->ecc.hwctl = jz4780_nand_ecc_hwctl;

		chip->ecc.calculate = jz4780_nand_ecc_calculate;

		chip->ecc.correct = jz4780_nand_ecc_correct;

		/* fall through */

	case NAND_ECC_SOFT:

	case NAND_ECC_SOFT_BCH:

		dev_info(dev, "using %s (strength %d, size %d, bytes %d)\n",

			(nfc->bch) ? "hardware BCH" : "software ECC",

			chip->ecc.strength, chip->ecc.size, chip->ecc.bytes);

	else

		break;

	case NAND_ECC_NONE:

		dev_info(dev, "not using ECC\n");

		break;

	default:

		dev_err(dev, "ECC mode %d not supported\n", chip->ecc.mode);

		return -EINVAL;

	}



	/* The NAND core will generate the ECC layout. */

	if (chip->ecc.mode == NAND_ECC_SOFT || chip->ecc.mode == NAND_ECC_SOFT_BCH)

	/* The NAND core will generate the ECC layout for SW ECC */

	if (chip->ecc.mode != NAND_ECC_HW)

		return 0;



	/* Generate ECC layout. ECC codes are right aligned in the OOB area. */