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Commit 909ceef6 authored by Thomas Abraham's avatar Thomas Abraham Committed by Kukjin Kim
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ARM: SAMSUNG: remove sdhci default configuration setup platform helper 



The sdhci platform helper function that sets up the default controller
configuration is removed for all Samsung platforms since such default
controller configuration can be handled by the driver.

Cc: Ben Dooks <ben-linux@fluff.org>
Signed-off-by: default avatarThomas Abraham <thomas.abraham@linaro.org>
Signed-off-by: default avatarKukjin Kim <kgene.kim@samsung.com>
parent 4c59de05

arch/arm/mach-exynos4/setup-sdhci.c

+0 −47
Original line number Diff line number Diff line
@@ -10,16 +10,7 @@ 
 * published by the Free Software Foundation.

*/



#include <linux/kernel.h>

#include <linux/types.h>

#include <linux/interrupt.h>

#include <linux/platform_device.h>

#include <linux/io.h>



#include <linux/mmc/card.h>

#include <linux/mmc/host.h>



#include <plat/regs-sdhci.h>



/* clock sources for the mmc bus clock, order as for the ctrl2[5..4] */
@@ -29,41 +20,3 @@ char *exynos4_hsmmc_clksrcs[4] = { 
	[2] = "sclk_mmc",	/* mmc_bus */

	[3] = NULL,

};
 


void exynos4_setup_sdhci_cfg_card(struct platform_device *dev, void __iomem *r,

				  struct mmc_ios *ios, struct mmc_card *card)

{

	u32 ctrl2, ctrl3;



	/* don't need to alter anything according to card-type */



	ctrl2 = readl(r + S3C_SDHCI_CONTROL2);



	/* select base clock source to HCLK */



	ctrl2 &= S3C_SDHCI_CTRL2_SELBASECLK_MASK;



	/*

	 * clear async mode, enable conflict mask, rx feedback ctrl, SD

	 * clk hold and no use debounce count

	 */



	ctrl2 |= (S3C64XX_SDHCI_CTRL2_ENSTAASYNCCLR |

		  S3C64XX_SDHCI_CTRL2_ENCMDCNFMSK |

		  S3C_SDHCI_CTRL2_ENFBCLKRX |

		  S3C_SDHCI_CTRL2_DFCNT_NONE |

		  S3C_SDHCI_CTRL2_ENCLKOUTHOLD);



	/* Tx and Rx feedback clock delay control */



	if (ios->clock < 25 * 1000000)

		ctrl3 = (S3C_SDHCI_CTRL3_FCSEL3 |

			 S3C_SDHCI_CTRL3_FCSEL2 |

			 S3C_SDHCI_CTRL3_FCSEL1 |

			 S3C_SDHCI_CTRL3_FCSEL0);

	else

		ctrl3 = (S3C_SDHCI_CTRL3_FCSEL1 | S3C_SDHCI_CTRL3_FCSEL0);



	writel(ctrl2, r + S3C_SDHCI_CONTROL2);

	writel(ctrl3, r + S3C_SDHCI_CONTROL3);

}

arch/arm/mach-s3c2416/setup-sdhci.c

+0 −37
Original line number Diff line number Diff line
@@ -12,17 +12,7 @@ 
 * published by the Free Software Foundation.

*/



#include <linux/kernel.h>

#include <linux/types.h>

#include <linux/interrupt.h>

#include <linux/platform_device.h>

#include <linux/io.h>



#include <linux/mmc/card.h>

#include <linux/mmc/host.h>



#include <plat/regs-sdhci.h>

#include <plat/sdhci.h>



/* clock sources for the mmc bus clock, order as for the ctrl2[5..4] */
@@ -32,30 +22,3 @@ char *s3c2416_hsmmc_clksrcs[4] = { 
	[2] = "hsmmc-if",

	/* [3] = "48m", - note not successfully used yet */

};
 


void s3c2416_setup_sdhci_cfg_card(struct platform_device *dev,

				  void __iomem *r,

				  struct mmc_ios *ios,

				  struct mmc_card *card)

{

	u32 ctrl2, ctrl3;



	ctrl2 = __raw_readl(r + S3C_SDHCI_CONTROL2);

	ctrl2 &= S3C_SDHCI_CTRL2_SELBASECLK_MASK;

	ctrl2 |= (S3C64XX_SDHCI_CTRL2_ENSTAASYNCCLR |

		  S3C64XX_SDHCI_CTRL2_ENCMDCNFMSK |

		  S3C_SDHCI_CTRL2_ENFBCLKRX |

		  S3C_SDHCI_CTRL2_DFCNT_NONE |

		  S3C_SDHCI_CTRL2_ENCLKOUTHOLD);



	if (ios->clock < 25 * 1000000)

		ctrl3 = (S3C_SDHCI_CTRL3_FCSEL3 |

			 S3C_SDHCI_CTRL3_FCSEL2 |

			 S3C_SDHCI_CTRL3_FCSEL1 |

			 S3C_SDHCI_CTRL3_FCSEL0);

	else

		ctrl3 = (S3C_SDHCI_CTRL3_FCSEL1 | S3C_SDHCI_CTRL3_FCSEL0);



	__raw_writel(ctrl2, r + S3C_SDHCI_CONTROL2);

	__raw_writel(ctrl3, r + S3C_SDHCI_CONTROL3);

}

arch/arm/mach-s3c64xx/setup-sdhci.c

+0 −48
Original line number Diff line number Diff line
@@ -12,17 +12,7 @@ 
 * published by the Free Software Foundation.

*/



#include <linux/kernel.h>

#include <linux/types.h>

#include <linux/interrupt.h>

#include <linux/platform_device.h>

#include <linux/io.h>



#include <linux/mmc/card.h>

#include <linux/mmc/host.h>



#include <plat/regs-sdhci.h>

#include <plat/sdhci.h>



/* clock sources for the mmc bus clock, order as for the ctrl2[5..4] */
@@ -32,41 +22,3 @@ char *s3c64xx_hsmmc_clksrcs[4] = { 
	[2] = "mmc_bus",

	/* [3] = "48m", - note not successfully used yet */

};
 


void s3c6400_setup_sdhci_cfg_card(struct platform_device *dev,

				  void __iomem *r,

				  struct mmc_ios *ios,

				  struct mmc_card *card)

{

	u32 ctrl2, ctrl3;



	ctrl2 = readl(r + S3C_SDHCI_CONTROL2);

	ctrl2 &= S3C_SDHCI_CTRL2_SELBASECLK_MASK;

	ctrl2 |= (S3C64XX_SDHCI_CTRL2_ENSTAASYNCCLR |

		  S3C64XX_SDHCI_CTRL2_ENCMDCNFMSK |

		  S3C_SDHCI_CTRL2_ENFBCLKRX |

		  S3C_SDHCI_CTRL2_DFCNT_NONE |

		  S3C_SDHCI_CTRL2_ENCLKOUTHOLD);



	if (ios->clock < 25 * 1000000)

		ctrl3 = (S3C_SDHCI_CTRL3_FCSEL3 |

			 S3C_SDHCI_CTRL3_FCSEL2 |

			 S3C_SDHCI_CTRL3_FCSEL1 |

			 S3C_SDHCI_CTRL3_FCSEL0);

	else

		ctrl3 = (S3C_SDHCI_CTRL3_FCSEL1 | S3C_SDHCI_CTRL3_FCSEL0);



	pr_debug("%s: CTRL 2=%08x, 3=%08x\n", __func__, ctrl2, ctrl3);

	writel(ctrl2, r + S3C_SDHCI_CONTROL2);

	writel(ctrl3, r + S3C_SDHCI_CONTROL3);

}



void s3c6410_setup_sdhci_cfg_card(struct platform_device *dev,

				  void __iomem *r,

				  struct mmc_ios *ios,

				  struct mmc_card *card)

{

	writel(S3C64XX_SDHCI_CONTROL4_DRIVE_9mA, r + S3C64XX_SDHCI_CONTROL4);



	s3c6400_setup_sdhci_cfg_card(dev, r, ios, card);

}

arch/arm/mach-s5pc100/setup-sdhci.c

+0 −42
Original line number Diff line number Diff line
@@ -11,17 +11,7 @@ 
 * published by the Free Software Foundation.

*/



#include <linux/kernel.h>

#include <linux/types.h>

#include <linux/interrupt.h>

#include <linux/platform_device.h>

#include <linux/io.h>



#include <linux/mmc/card.h>

#include <linux/mmc/host.h>



#include <plat/regs-sdhci.h>

#include <plat/sdhci.h>



/* clock sources for the mmc bus clock, order as for the ctrl2[5..4] */
@@ -31,35 +21,3 @@ char *s5pc100_hsmmc_clksrcs[4] = { 
	[2] = "sclk_mmc",	/* mmc_bus */

	/* [3] = "48m",		- note not successfully used yet */

};
 




void s5pc100_setup_sdhci0_cfg_card(struct platform_device *dev,

				    void __iomem *r,

				    struct mmc_ios *ios,

				    struct mmc_card *card)

{

	u32 ctrl2, ctrl3;



	/* don't need to alter anything according to card-type */



	writel(S3C64XX_SDHCI_CONTROL4_DRIVE_9mA, r + S3C64XX_SDHCI_CONTROL4);



	ctrl2 = readl(r + S3C_SDHCI_CONTROL2);

	ctrl2 &= S3C_SDHCI_CTRL2_SELBASECLK_MASK;

	ctrl2 |= (S3C64XX_SDHCI_CTRL2_ENSTAASYNCCLR |

		  S3C64XX_SDHCI_CTRL2_ENCMDCNFMSK |

		  S3C_SDHCI_CTRL2_ENFBCLKRX |

		  S3C_SDHCI_CTRL2_DFCNT_NONE |

		  S3C_SDHCI_CTRL2_ENCLKOUTHOLD);



	if (ios->clock < 25 * 1000000)

		ctrl3 = (S3C_SDHCI_CTRL3_FCSEL3 |

			 S3C_SDHCI_CTRL3_FCSEL2 |

			 S3C_SDHCI_CTRL3_FCSEL1 |

			 S3C_SDHCI_CTRL3_FCSEL0);

	else

		ctrl3 = (S3C_SDHCI_CTRL3_FCSEL1 | S3C_SDHCI_CTRL3_FCSEL0);



	writel(ctrl2, r + S3C_SDHCI_CONTROL2);

	writel(ctrl3, r + S3C_SDHCI_CONTROL3);

}

arch/arm/mach-s5pv210/setup-sdhci.c

+0 −41
Original line number Diff line number Diff line
@@ -10,17 +10,7 @@ 
 * published by the Free Software Foundation.

*/



#include <linux/kernel.h>

#include <linux/types.h>

#include <linux/interrupt.h>

#include <linux/platform_device.h>

#include <linux/io.h>



#include <linux/mmc/card.h>

#include <linux/mmc/host.h>



#include <plat/regs-sdhci.h>

#include <plat/sdhci.h>



/* clock sources for the mmc bus clock, order as for the ctrl2[5..4] */
@@ -30,34 +20,3 @@ char *s5pv210_hsmmc_clksrcs[4] = { 
	[2] = "sclk_mmc",	/* mmc_bus */

	/* [3] = NULL,		- reserved */

};
 


void s5pv210_setup_sdhci_cfg_card(struct platform_device *dev,

				    void __iomem *r,

				    struct mmc_ios *ios,

				    struct mmc_card *card)

{

	u32 ctrl2, ctrl3;



	/* don't need to alter anything according to card-type */



	writel(S3C64XX_SDHCI_CONTROL4_DRIVE_9mA, r + S3C64XX_SDHCI_CONTROL4);



	ctrl2 = readl(r + S3C_SDHCI_CONTROL2);

	ctrl2 &= S3C_SDHCI_CTRL2_SELBASECLK_MASK;

	ctrl2 |= (S3C64XX_SDHCI_CTRL2_ENSTAASYNCCLR |

		  S3C64XX_SDHCI_CTRL2_ENCMDCNFMSK |

		  S3C_SDHCI_CTRL2_ENFBCLKRX |

		  S3C_SDHCI_CTRL2_DFCNT_NONE |

		  S3C_SDHCI_CTRL2_ENCLKOUTHOLD);



	if (ios->clock < 25 * 1000000)

		ctrl3 = (S3C_SDHCI_CTRL3_FCSEL3 |

			 S3C_SDHCI_CTRL3_FCSEL2 |

			 S3C_SDHCI_CTRL3_FCSEL1 |

			 S3C_SDHCI_CTRL3_FCSEL0);

	else

		ctrl3 = (S3C_SDHCI_CTRL3_FCSEL1 | S3C_SDHCI_CTRL3_FCSEL0);



	writel(ctrl2, r + S3C_SDHCI_CONTROL2);

	writel(ctrl3, r + S3C_SDHCI_CONTROL3);

}