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Commit 90996511 authored by Paul Burton's avatar Paul Burton Committed by Ralf Baechle
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MIPS: CPS: use 32b accesses to GCRs 



Commit b677bc03 ("MIPS: cps-vec: Use macros for various arithmetics
and memory operations") replaced various load & store instructions
through cps-vec.S with the PTR_L & PTR_S macros. However it was somewhat
overzealous in doing so for CM GCR accesses, since the bit width of the
CM doesn't necessarily match that of the CPU. The registers accessed
(GCR_CL_COHERENCE & GCR_CL_ID) should be safe to simply always access
using 32b instructions, so do so in order to avoid issues when using a
32b CM with a 64b CPU.

Signed-off-by: default avatarPaul Burton <paul.burton@imgtec.com>
Cc: Markos Chandras <markos.chandras@imgtec.com>
Cc: <stable@vger.kernel.org> # 3.16+
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Cc: James Hogan <james.hogan@imgtec.com>
Patchwork: https://patchwork.linux-mips.org/patch/10864/


Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
parent c13dcf9f

arch/mips/kernel/cps-vec.S

+2 −2
Original line number Diff line number Diff line
@@ -152,7 +152,7 @@ dcache_done: 


	/* Enter the coherent domain */

	li	t0, 0xff

	PTR_S	t0, GCR_CL_COHERENCE_OFS(v1)

	sw	t0, GCR_CL_COHERENCE_OFS(v1)

	ehb



	/* Jump to kseg0 */
@@ -302,7 +302,7 @@ LEAF(mips_cps_boot_vpes) 
	PTR_L	t0, 0(t0)



	/* Calculate a pointer to this cores struct core_boot_config */

	PTR_L	t0, GCR_CL_ID_OFS(t0)

	lw	t0, GCR_CL_ID_OFS(t0)

	li	t1, COREBOOTCFG_SIZE

	mul	t0, t0, t1

	PTR_LA	t1, mips_cps_core_bootcfg