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Commit 902d9e0f authored by Rafał Miłecki's avatar Rafał Miłecki Committed by John W. Linville
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ssb: check for flash presentence 



We can not assume parallel flash is always present, there are boards
with *serial* flash and probably some without flash at all.
Define some bits by the way.

Signed-off-by: default avatarRafał Miłecki <zajec5@gmail.com>
Reviewed-by: default avatarHauke Mehrtens <hauke@hauke-m.de>
Signed-off-by: default avatarJohn W. Linville <linville@tuxdriver.com>
parent 85ce5ae5

drivers/ssb/driver_mipscore.c

+21 −7
Original line number Diff line number Diff line
@@ -190,16 +190,30 @@ static void ssb_mips_flash_detect(struct ssb_mipscore *mcore) 
{

	struct ssb_bus *bus = mcore->dev->bus;



	/* When there is no chipcommon on the bus there is 4MB flash */

	if (!bus->chipco.dev) {

		mcore->flash_buswidth = 2;

	if (bus->chipco.dev) {

		mcore->flash_window = 0x1c000000;

		mcore->flash_window_size = 0x02000000;

		mcore->flash_window = SSB_FLASH1;

		mcore->flash_window_size = SSB_FLASH1_SZ;

		return;

	}



	/* There is ChipCommon, so use it to read info about flash */

	switch (bus->chipco.capabilities & SSB_CHIPCO_CAP_FLASHT) {

	case SSB_CHIPCO_FLASHT_STSER:

	case SSB_CHIPCO_FLASHT_ATSER:

		pr_err("Serial flash not supported\n");

		break;

	case SSB_CHIPCO_FLASHT_PARA:

		pr_debug("Found parallel flash\n");

		mcore->flash_window = SSB_FLASH2;

		mcore->flash_window_size = SSB_FLASH2_SZ;

		if ((ssb_read32(bus->chipco.dev, SSB_CHIPCO_FLASH_CFG)

		               & SSB_CHIPCO_CFG_DS16) == 0)

			mcore->flash_buswidth = 1;

	} else {

		mcore->flash_window = 0x1fc00000;

		mcore->flash_window_size = 0x00400000;

		else

			mcore->flash_buswidth = 2;

		break;

	}

}

include/linux/ssb/ssb_driver_chipcommon.h

+3 −1
Original line number Diff line number Diff line
@@ -504,7 +504,9 @@ 
#define SSB_CHIPCO_FLASHCTL_ST_SE	0x02D8		/* Sector Erase */

#define SSB_CHIPCO_FLASHCTL_ST_BE	0x00C7		/* Bulk Erase */

#define SSB_CHIPCO_FLASHCTL_ST_DP	0x00B9		/* Deep Power-down */

#define SSB_CHIPCO_FLASHCTL_ST_RSIG	0x03AB		/* Read Electronic Signature */

#define SSB_CHIPCO_FLASHCTL_ST_RES	0x03AB		/* Read Electronic Signature */

#define SSB_CHIPCO_FLASHCTL_ST_CSA	0x1000		/* Keep chip select asserted */

#define SSB_CHIPCO_FLASHCTL_ST_SSE	0x0220		/* Sub-sector Erase */



/* Status register bits for ST flashes */

#define SSB_CHIPCO_FLASHSTA_ST_WIP	0x01		/* Write In Progress */