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Commit 900af53f authored by Satyajit Desai's avatar Satyajit Desai Committed by Gerrit - the friendly Code Review server
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ARM: dts: msm: Add DDR CTI for SDM845 



Add DDR CTI to the device tree for SDM845. This component will be
used to generate cross triggers for the DDR sub-system.

Change-Id: I74327a14a38beb73122f799985a7fd8a4b8f5fd8
Signed-off-by: default avatarSatyajit Desai <sadesai@codeaurora.org>
parent 7fc1bbb1

arch/arm64/boot/dts/qcom/sdm845-coresight.dtsi

+24 −0
Original line number Diff line number Diff line
@@ -1279,6 +1279,30 @@ 
		};

	};



	cti_ddr0: cti@69e1000 {

		compatible = "arm,primecell";

		arm,primecell-periphid = <0x0003b969>;

		reg = <0x69e1000 0x1000>;

		reg-names = "cti-base";



		coresight-name = "coresight-cti-ddr0";



		clocks = <&clock_aop QDSS_CLK>;

		clock-names = "apb_pclk";

	};



	cti_ddr1: cti@69e4000 {

		compatible = "arm,primecell";

		arm,primecell-periphid = <0x0003b969>;

		reg = <0x69e4000 0x1000>;

		reg-names = "cti-base";



		coresight-name = "coresight-cti-ddr1";



		clocks = <&clock_aop QDSS_CLK>;

		clock-names = "apb_pclk";

	};



	cti0: cti@6010000 {

		compatible = "arm,primecell";

		arm,primecell-periphid = <0x0003b966>;