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Commit 8fff6e38 authored by Casey Piper's avatar Casey Piper Committed by Narendra Muppalla
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clk: msm: hdmi: Increase PLL ready bit timeout 



When using 4k resolutions at 60fps, the PLL
ready bit will take slightly longer than other
video modes. Increase the timeout value to
ensure that the PLL lock is successful. Also
modify the lane mode values to improve Shmoo
margin with low core voltage.

Change-Id: I9d65535b941e755fe706e4dd61cb357a7a62cdc2
Signed-off-by: default avatarCasey Piper <cpiper@codeaurora.org>
parent 1b3a6200

drivers/clk/qcom/mdss/mdss-hdmi-pll-8996.c

+3 −3
Original line number Diff line number Diff line
@@ -318,7 +318,7 @@ 
#define HDMI_PHY_PHY_REVISION_ID3             (0xC4)



#define HDMI_PLL_POLL_MAX_READS                2500

#define HDMI_PLL_POLL_TIMEOUT_US               100000

#define HDMI_PLL_POLL_TIMEOUT_US               150000



enum hdmi_pll_freqs {

	HDMI_PCLK_25200_KHZ,
@@ -1419,8 +1419,8 @@ static int hdmi_8996_v3_calculate(u32 pix_clk, 
	cfg->phy_mode = (bclk > HDMI_HIGH_FREQ_BIT_CLK_THRESHOLD) ? 0x10 : 0x0;

	cfg->com_vco_tune_ctrl = 0x0;



	cfg->tx_l0_lane_mode = (pd.half_rate_mode ? 0x7 : 0x3);

	cfg->tx_l2_lane_mode = (pd.half_rate_mode ? 0x7 : 0x3);

	cfg->tx_l0_lane_mode = 0x43;

	cfg->tx_l2_lane_mode = 0x43;



	if (bclk > HDMI_HIGH_FREQ_BIT_CLK_THRESHOLD) {

		cfg->tx_l0_tx_drv_lvl = 0x25;