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Commit 8fe58df0 authored by Kyle Piefer's avatar Kyle Piefer Committed by Gerrit - the friendly Code Review server
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msm: kgsl: Surround RBBM interrupt mask writes with OOBs 



RBBM interrupt mask register is in the GX domain so it
will not be accessible during IFPC. Surround it with OOBs
to prevent unwanted power collapses.

CRs-Fixed: 2085877
Change-Id: I07ad9db9cb0b8ad6226e95c358c738c382bffc04
Signed-off-by: default avatarKyle Piefer <kpiefer@codeaurora.org>
parent 83656c8c

drivers/gpu/msm/adreno.c

+33 −11
Original line number Diff line number Diff line
@@ -554,7 +554,13 @@ static int _soft_reset(struct adreno_device *adreno_dev) 
	return 0;

}





/**

 * adreno_irqctrl() - Enables/disables the RBBM interrupt mask

 * @adreno_dev: Pointer to an adreno_device

 * @state: 1 for masked or 0 for unmasked

 * Power: The caller of this function must make sure to use OOBs

 * so that we know that the GPU is powered on

 */

void adreno_irqctrl(struct adreno_device *adreno_dev, int state)

{

	struct adreno_gpudev *gpudev = ADRENO_GPU_DEVICE(adreno_dev);
@@ -1509,9 +1515,9 @@ static int _adreno_start(struct adreno_device *adreno_dev) 


	/* Send OOB request to turn on the GX */

	if (gpudev->oob_set) {

		status = gpudev->oob_set(adreno_dev, OOB_GPUSTART_SET_MASK,

				OOB_GPUSTART_CHECK_MASK,

				OOB_GPUSTART_CLEAR_MASK);

		status = gpudev->oob_set(adreno_dev, OOB_GPU_SET_MASK,

				OOB_GPU_CHECK_MASK,

				OOB_GPU_CLEAR_MASK);

		if (status)

			goto error_mmu_off;

	}
@@ -1611,7 +1617,7 @@ static int _adreno_start(struct adreno_device *adreno_dev) 


	/* Send OOB request to allow IFPC */

	if (gpudev->oob_clear) {

		gpudev->oob_clear(adreno_dev, OOB_GPUSTART_CLEAR_MASK);

		gpudev->oob_clear(adreno_dev, OOB_GPU_CLEAR_MASK);



		/* If we made it this far, the BOOT OOB was sent to the GMU */

		if (ADRENO_QUIRK(adreno_dev, ADRENO_QUIRK_HFI_USE_REG))
@@ -1622,15 +1628,16 @@ static int _adreno_start(struct adreno_device *adreno_dev) 
	return 0;



error_oob_clear:

	if (gpudev->oob_clear) {

		gpudev->oob_clear(adreno_dev, OOB_GPUSTART_CLEAR_MASK);

		if (ADRENO_QUIRK(adreno_dev, ADRENO_QUIRK_HFI_USE_REG))

			gpudev->oob_clear(adreno_dev,

					OOB_BOOT_SLUMBER_CLEAR_MASK);

	}

	if (gpudev->oob_clear)

		gpudev->oob_clear(adreno_dev, OOB_GPU_CLEAR_MASK);



error_mmu_off:

	kgsl_mmu_stop(&device->mmu);

	if (gpudev->oob_clear &&

			ADRENO_QUIRK(adreno_dev, ADRENO_QUIRK_HFI_USE_REG)) {

		gpudev->oob_clear(adreno_dev,

				OOB_BOOT_SLUMBER_CLEAR_MASK);

	}



error_pwr_off:

	/* set the state back to original state */
@@ -1689,10 +1696,22 @@ static int adreno_stop(struct kgsl_device *device) 
{

	struct adreno_device *adreno_dev = ADRENO_DEVICE(device);

	struct adreno_gpudev *gpudev = ADRENO_GPU_DEVICE(adreno_dev);

	int error = 0;



	if (!test_bit(ADRENO_DEVICE_STARTED, &adreno_dev->priv))

		return 0;



	/* Turn the power on one last time before stopping */

	if (gpudev->oob_set) {

		error = gpudev->oob_set(adreno_dev, OOB_GPU_SET_MASK,

				OOB_GPU_CHECK_MASK,

				OOB_GPU_CLEAR_MASK);

		if (error) {

			gpudev->oob_clear(adreno_dev, OOB_GPU_CLEAR_MASK);

			return error;

		}

	}



	adreno_set_active_ctxs_null(adreno_dev);



	adreno_dispatcher_stop(adreno_dev);
@@ -1716,6 +1735,9 @@ static int adreno_stop(struct kgsl_device *device) 
	/* Save physical performance counter values before GPU power down*/

	adreno_perfcounter_save(adreno_dev);



	if (gpudev->oob_clear)

		gpudev->oob_clear(adreno_dev, OOB_GPU_CLEAR_MASK);



	/*

	 * Saving perfcounters will use an OOB to put the GMU into

	 * active state. Before continuing, we should wait for the

drivers/gpu/msm/adreno_sysfs.c

+0 −1
Original line number Diff line number Diff line
@@ -165,7 +165,6 @@ static int _ft_hang_intr_status_store(struct adreno_device *adreno_dev, 


	if (test_bit(ADRENO_DEVICE_STARTED, &adreno_dev->priv)) {

		kgsl_pwrctrl_change_state(device, KGSL_STATE_ACTIVE);

		adreno_irqctrl(adreno_dev, 1);

	} else if (device->state == KGSL_STATE_INIT) {

		ret = -EACCES;

		change_bit(ADRENO_DEVICE_HANG_INTR, &adreno_dev->priv);

drivers/gpu/msm/kgsl_gmu.h

+3 −3
Original line number Diff line number Diff line
@@ -76,9 +76,9 @@ 
#define OOB_PERFCNTR_SET_MASK		BIT(17)

#define OOB_PERFCNTR_CHECK_MASK		BIT(25)

#define OOB_PERFCNTR_CLEAR_MASK		BIT(25)

#define OOB_GPUSTART_SET_MASK		BIT(18)

#define OOB_GPUSTART_CHECK_MASK		BIT(26)

#define OOB_GPUSTART_CLEAR_MASK		BIT(26)

#define OOB_GPU_SET_MASK		BIT(18)

#define OOB_GPU_CHECK_MASK		BIT(26)

#define OOB_GPU_CLEAR_MASK		BIT(26)



/* Bits for the flags field in the gmu structure */

enum gmu_flags {