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Commit 8f2c59f0 authored by Ben Widawsky's avatar Ben Widawsky Committed by Daniel Vetter
Browse files

drm/i915: Add dev to ppgtt 



Some subsequent commits will need to know what generation we're running
on to do different pte encoding for the ppgtt. Since it's not much
hassle or overhead to store it in the ppgtt structure, do that.

Signed-off-by: default avatarBen Widawsky <ben@bwidawsk.net>
Reviewed-by: default avatarJesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent 8693607a

drivers/gpu/drm/i915/i915_drv.h

+1 −0
Original line number Diff line number Diff line
@@ -345,6 +345,7 @@ struct intel_device_info { 
#define I915_PPGTT_PD_ENTRIES 512

#define I915_PPGTT_PT_ENTRIES 1024

struct i915_hw_ppgtt {

	struct drm_device *dev;

	unsigned num_pd_entries;

	struct page **pt_pages;

	uint32_t pd_offset;

drivers/gpu/drm/i915/i915_gem_gtt.c

+3 −2
Original line number Diff line number Diff line
@@ -77,6 +77,7 @@ int i915_gem_init_aliasing_ppgtt(struct drm_device *dev) 
	if (!ppgtt)

		return ret;



	ppgtt->dev = dev;

	ppgtt->num_pd_entries = I915_PPGTT_PD_ENTRIES;

	ppgtt->pt_pages = kzalloc(sizeof(struct page *)*ppgtt->num_pd_entries,

				  GFP_KERNEL);
@@ -218,7 +219,7 @@ void i915_ppgtt_bind_object(struct i915_hw_ppgtt *ppgtt, 
	switch (cache_level) {

	case I915_CACHE_LLC_MLC:

		/* Haswell doesn't set L3 this way */

		if (IS_HASWELL(obj->base.dev))

		if (IS_HASWELL(ppgtt->dev))

			pte_flags |= GEN6_PTE_CACHE_LLC;

		else

			pte_flags |= GEN6_PTE_CACHE_LLC_MLC;
@@ -227,7 +228,7 @@ void i915_ppgtt_bind_object(struct i915_hw_ppgtt *ppgtt, 
		pte_flags |= GEN6_PTE_CACHE_LLC;

		break;

	case I915_CACHE_NONE:

		if (IS_HASWELL(obj->base.dev))

		if (IS_HASWELL(ppgtt->dev))

			pte_flags |= HSW_PTE_UNCACHED;

		else

			pte_flags |= GEN6_PTE_UNCACHED;