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Commit 8e6a11e2 authored by Vijayavardhan Vennapusa's avatar Vijayavardhan Vennapusa Committed by Mayank Rana
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USB: dwc3: msm: Fail probe if core-clk-rate is not passed from dts 



Currently USB driver is not failing probe if USB core-clk-rate property
is not exist. This leads to USB enumeration failures across connect/
disconnect. Hence make core-clk-rate property mandatory and if in case
not defined, fail the probe.

Also return error if dwc3_core_pre_init() fails during dwc3-msm_resume()
due to phy init fails and don't go ahead with setting up event buffers
as event buffers allocation is done.

Change-Id: I3927ad2f670e45acd10f8568857cf9f3434df657
Signed-off-by: default avatarVijayavardhan Vennapusa <vvreddy@codeaurora.org>
Signed-off-by: default avatarMayank Rana <mrana@codeaurora.org>
parent c4d66bde

drivers/usb/dwc3/dwc3-msm.c

+15 −19
Original line number Diff line number Diff line
@@ -1853,6 +1853,7 @@ static void dwc3_msm_power_collapse_por(struct dwc3_msm *mdwc) 
{

	struct dwc3 *dwc = platform_get_drvdata(mdwc->dwc3);

	u32 val;

	int ret;



	/* Configure AHB2PHY for one wait state read/write */

	if (mdwc->ahb2phy_base) {
@@ -1871,7 +1872,11 @@ static void dwc3_msm_power_collapse_por(struct dwc3_msm *mdwc) 
	if (!mdwc->init) {

		dbg_event(0xFF, "dwc3 init",

				atomic_read(&mdwc->dev->power.usage_count));

		dwc3_core_pre_init(dwc);

		ret = dwc3_core_pre_init(dwc);

		if (ret) {

			dev_err(mdwc->dev, "dwc3_core_pre_init failed\n");

			return;

		}

		mdwc->init = true;

	}
@@ -2478,28 +2483,19 @@ static int dwc3_msm_get_clk_gdsc(struct dwc3_msm *mdwc) 
		return PTR_ERR(mdwc->core_reset);

	}



	if (!of_property_read_u32(mdwc->dev->of_node, "qcom,core-clk-rate",

	if (of_property_read_u32(mdwc->dev->of_node, "qcom,core-clk-rate",

				(u32 *)&mdwc->core_clk_rate)) {

		mdwc->core_clk_rate = clk_round_rate(mdwc->core_clk,

							mdwc->core_clk_rate);

	} else {

		/*

		 * Get Max supported clk frequency for USB Core CLK and request

		 * to set the same.

		 */

		mdwc->core_clk_rate = clk_round_rate(mdwc->core_clk, LONG_MAX);

		dev_err(mdwc->dev, "USB core-clk-rate is not present\n");

		return -EINVAL;

	}



	if (IS_ERR_VALUE(mdwc->core_clk_rate)) {

		dev_err(mdwc->dev, "fail to get core clk max freq.\n");

	} else {

	mdwc->core_clk_rate = clk_round_rate(mdwc->core_clk,

							mdwc->core_clk_rate);

	dev_dbg(mdwc->dev, "USB core frequency = %ld\n",

						mdwc->core_clk_rate);

	ret = clk_set_rate(mdwc->core_clk, mdwc->core_clk_rate);

	if (ret)

			dev_err(mdwc->dev, "fail to set core_clk freq:%d\n",

									ret);

	}

		dev_err(mdwc->dev, "fail to set core_clk freq:%d\n", ret);



	if (of_property_read_u32(mdwc->dev->of_node, "qcom,core-clk-rate-hs",

				(u32 *)&mdwc->core_clk_rate_hs)) {