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Commit 8e37717d authored by Kyle Piefer's avatar Kyle Piefer Committed by Gerrit - the friendly Code Review server
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msm: kgsl: Update PDC sequence for A630 



A630 has changes to the PDC sequencer code.
Update the RSCC and PDC set up to include these
changes.

CRs-Fixed: 2085877
Change-Id: I9a58d385989a684eb449ab02a783dea3cfd9777f
Signed-off-by: default avatarKyle Piefer <kpiefer@codeaurora.org>
parent 3e1f6bce

drivers/gpu/msm/adreno_a6xx.c

+12 −7
Original line number Diff line number Diff line
@@ -888,8 +888,12 @@ static void _regwrite(void __iomem *regbase, 
 */

static void _load_gmu_rpmh_ucode(struct kgsl_device *device)

{

	struct adreno_device *adreno_dev = ADRENO_DEVICE(device);

	struct gmu_device *gmu = &device->gmu;



	/* Disable SDE clock gating */

	kgsl_gmu_regwrite(device, A6XX_GPU_RSCC_RSC_STATUS0_DRV0, BIT(24));



	/* Setup RSC PDC handshake for sleep and wakeup */

	kgsl_gmu_regwrite(device, A6XX_RSCC_PDC_SLAVE_ID_DRV0, 1);

	kgsl_gmu_regwrite(device, A6XX_RSCC_HIDDEN_TCS_CMD0_DATA, 0);
@@ -909,7 +913,8 @@ static void _load_gmu_rpmh_ucode(struct kgsl_device *device) 
	kgsl_gmu_regwrite(device, A6XX_RSCC_PDC_MATCH_VALUE_LO, 0x4510);

	kgsl_gmu_regwrite(device, A6XX_RSCC_PDC_MATCH_VALUE_HI, 0x4514);



	/* Enable timestamp event */

	/* Enable timestamp event for v1 only */

	if (adreno_is_a630v1(adreno_dev))

		kgsl_gmu_regwrite(device, A6XX_RSCC_TIMESTAMP_UNIT1_EN_DRV0, 1);



	/* Load RSC sequencer uCode for sleep and wakeup */
@@ -920,11 +925,11 @@ static void _load_gmu_rpmh_ucode(struct kgsl_device *device) 
	kgsl_gmu_regwrite(device, A6XX_RSCC_SEQ_MEM_0_DRV0 + 4, 0x0020E8A8);



	/* Load PDC sequencer uCode for power up and power down sequence */

	_regwrite(gmu->pdc_reg_virt, PDC_GPU_SEQ_MEM_0, 0xFFBFA1E1);

	_regwrite(gmu->pdc_reg_virt, PDC_GPU_SEQ_MEM_0 + 1, 0xE0A4A3A2);

	_regwrite(gmu->pdc_reg_virt, PDC_GPU_SEQ_MEM_0 + 2, 0xE2848382);

	_regwrite(gmu->pdc_reg_virt, PDC_GPU_SEQ_MEM_0 + 3, 0xFDBDE4E3);

	_regwrite(gmu->pdc_reg_virt, PDC_GPU_SEQ_MEM_0 + 4, 0x00002081);

	_regwrite(gmu->pdc_reg_virt, PDC_GPU_SEQ_MEM_0, 0xFEBEA1E1);

	_regwrite(gmu->pdc_reg_virt, PDC_GPU_SEQ_MEM_0 + 1, 0xA5A4A3A2);

	_regwrite(gmu->pdc_reg_virt, PDC_GPU_SEQ_MEM_0 + 2, 0x8382A6E0);

	_regwrite(gmu->pdc_reg_virt, PDC_GPU_SEQ_MEM_0 + 3, 0xBCE3E284);

	_regwrite(gmu->pdc_reg_virt, PDC_GPU_SEQ_MEM_0 + 4, 0x002081FC);



	/* Set TCS commands used by PDC sequence for low power modes */

	_regwrite(gmu->pdc_reg_virt, PDC_GPU_TCS0_CMD_ENABLE_BANK, 7);