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Commit 8e042210 authored by Paul Mundt's avatar Paul Mundt
Browse files

Merge branch 'sh/stable-updates'

parents 9ad62ec4 2c940db2

Documentation/fault-injection/fault-injection.txt

+2 −2
Original line number Diff line number Diff line
@@ -143,8 +143,8 @@ o provide a way to configure fault attributes 
  failslab, fail_page_alloc, and fail_make_request use this way.

  Helper functions:



	init_fault_attr_entries(entries, attr, name);

	void cleanup_fault_attr_entries(entries);

	init_fault_attr_dentries(entries, attr, name);

	void cleanup_fault_attr_dentries(entries);



- module parameters

arch/arm/Kconfig

+1 −0
Original line number Diff line number Diff line
@@ -702,6 +702,7 @@ config ARCH_OMAP 
	select ARCH_HAS_CPUFREQ

	select GENERIC_TIME

	select GENERIC_CLOCKEVENTS

	select ARCH_HAS_HOLES_MEMORYMODEL

	help

	  Support for TI's OMAP platform (OMAP1 and OMAP2).

arch/arm/Makefile

+1 −1
Original line number Diff line number Diff line
@@ -94,7 +94,7 @@ CFLAGS_ABI +=-funwind-tables 
endif



ifeq ($(CONFIG_THUMB2_KERNEL),y)

AFLAGS_AUTOIT	:=$(call as-option,-Wa$(comma)-mimplicit-it=thumb,-Wa$(comma)-mauto-it)

AFLAGS_AUTOIT	:=$(call as-option,-Wa$(comma)-mimplicit-it=always,-Wa$(comma)-mauto-it)

AFLAGS_NOWARN	:=$(call as-option,-Wa$(comma)-mno-warn-deprecated,-Wa$(comma)-W)

CFLAGS_THUMB2	:=-mthumb $(AFLAGS_AUTOIT) $(AFLAGS_NOWARN)

AFLAGS_THUMB2	:=$(CFLAGS_THUMB2) -Wa$(comma)-mthumb

arch/arm/mach-mx25/clock.c

+37 −21
Original line number Diff line number Diff line
@@ -119,6 +119,11 @@ static unsigned long get_rate_nfc(struct clk *clk) 
	return get_rate_per(8);

}



static unsigned long get_rate_gpt(struct clk *clk)

{

	return get_rate_per(5);

}



static unsigned long get_rate_otg(struct clk *clk)

{

	return 48000000; /* FIXME */
@@ -144,7 +149,7 @@ static void clk_cgcr_disable(struct clk *clk) 
	__raw_writel(reg, clk->enable_reg);

}



#define DEFINE_CLOCK(name, i, er, es, gr, sr)		\

#define DEFINE_CLOCK(name, i, er, es, gr, sr, s)	\

	static struct clk name = {			\

		.id		= i,			\

		.enable_reg	= CRM_BASE + er,	\
@@ -153,27 +158,30 @@ static void clk_cgcr_disable(struct clk *clk) 
		.set_rate	= sr,			\

		.enable		= clk_cgcr_enable,	\

		.disable	= clk_cgcr_disable,	\

		.secondary	= s,			\

	}



DEFINE_CLOCK(gpt_clk,    0, CCM_CGCR0,  5, get_rate_ipg, NULL);

DEFINE_CLOCK(cspi1_clk,  0, CCM_CGCR1,  5, get_rate_ipg, NULL);

DEFINE_CLOCK(cspi2_clk,  0, CCM_CGCR1,  6, get_rate_ipg, NULL);

DEFINE_CLOCK(cspi3_clk,  0, CCM_CGCR1,  7, get_rate_ipg, NULL);

DEFINE_CLOCK(uart1_clk,  0, CCM_CGCR2, 14, get_rate_uart, NULL);

DEFINE_CLOCK(uart2_clk,  0, CCM_CGCR2, 15, get_rate_uart, NULL);

DEFINE_CLOCK(uart3_clk,  0, CCM_CGCR2, 16, get_rate_uart, NULL);

DEFINE_CLOCK(uart4_clk,  0, CCM_CGCR2, 17, get_rate_uart, NULL);

DEFINE_CLOCK(uart5_clk,  0, CCM_CGCR2, 18, get_rate_uart, NULL);

DEFINE_CLOCK(nfc_clk,    0, CCM_CGCR0,  8, get_rate_nfc, NULL);

DEFINE_CLOCK(usbotg_clk, 0, CCM_CGCR0, 28, get_rate_otg, NULL);

DEFINE_CLOCK(pwm1_clk,	 0, CCM_CGCR1, 31, get_rate_ipg, NULL);

DEFINE_CLOCK(pwm2_clk,	 0, CCM_CGCR2,  0, get_rate_ipg, NULL);

DEFINE_CLOCK(pwm3_clk,	 0, CCM_CGCR2,  1, get_rate_ipg, NULL);

DEFINE_CLOCK(pwm4_clk,	 0, CCM_CGCR2,  2, get_rate_ipg, NULL);

DEFINE_CLOCK(kpp_clk,	 0, CCM_CGCR1, 28, get_rate_ipg, NULL);

DEFINE_CLOCK(tsc_clk,	 0, CCM_CGCR2, 13, get_rate_ipg, NULL);

DEFINE_CLOCK(i2c_clk,	 0, CCM_CGCR0,  6, get_rate_i2c, NULL);

DEFINE_CLOCK(fec_clk,	 0, CCM_CGCR0, 23, get_rate_ipg, NULL);

DEFINE_CLOCK(gpt_clk,    0, CCM_CGCR0,  5, get_rate_gpt, NULL, NULL);

DEFINE_CLOCK(uart_per_clk, 0, CCM_CGCR0, 15, get_rate_uart, NULL, NULL);

DEFINE_CLOCK(cspi1_clk,  0, CCM_CGCR1,  5, get_rate_ipg, NULL, NULL);

DEFINE_CLOCK(cspi2_clk,  0, CCM_CGCR1,  6, get_rate_ipg, NULL, NULL);

DEFINE_CLOCK(cspi3_clk,  0, CCM_CGCR1,  7, get_rate_ipg, NULL, NULL);

DEFINE_CLOCK(fec_ahb_clk, 0, CCM_CGCR0, 23, NULL,	 NULL, NULL);

DEFINE_CLOCK(uart1_clk,  0, CCM_CGCR2, 14, get_rate_uart, NULL, &uart_per_clk);

DEFINE_CLOCK(uart2_clk,  0, CCM_CGCR2, 15, get_rate_uart, NULL, &uart_per_clk);

DEFINE_CLOCK(uart3_clk,  0, CCM_CGCR2, 16, get_rate_uart, NULL, &uart_per_clk);

DEFINE_CLOCK(uart4_clk,  0, CCM_CGCR2, 17, get_rate_uart, NULL, &uart_per_clk);

DEFINE_CLOCK(uart5_clk,  0, CCM_CGCR2, 18, get_rate_uart, NULL, &uart_per_clk);

DEFINE_CLOCK(nfc_clk,    0, CCM_CGCR0,  8, get_rate_nfc, NULL, NULL);

DEFINE_CLOCK(usbotg_clk, 0, CCM_CGCR0, 28, get_rate_otg, NULL, NULL);

DEFINE_CLOCK(pwm1_clk,	 0, CCM_CGCR1, 31, get_rate_ipg, NULL, NULL);

DEFINE_CLOCK(pwm2_clk,	 0, CCM_CGCR2,  0, get_rate_ipg, NULL, NULL);

DEFINE_CLOCK(pwm3_clk,	 0, CCM_CGCR2,  1, get_rate_ipg, NULL, NULL);

DEFINE_CLOCK(pwm4_clk,	 0, CCM_CGCR2,  2, get_rate_ipg, NULL, NULL);

DEFINE_CLOCK(kpp_clk,	 0, CCM_CGCR1, 28, get_rate_ipg, NULL, NULL);

DEFINE_CLOCK(tsc_clk,	 0, CCM_CGCR2, 13, get_rate_ipg, NULL, NULL);

DEFINE_CLOCK(i2c_clk,	 0, CCM_CGCR0,  6, get_rate_i2c, NULL, NULL);

DEFINE_CLOCK(fec_clk,	 0, CCM_CGCR1, 15, get_rate_ipg, NULL, &fec_ahb_clk);



#define _REGISTER_CLOCK(d, n, c)	\

	{				\
@@ -208,13 +216,21 @@ static struct clk_lookup lookups[] = { 
	_REGISTER_CLOCK("fec.0", NULL, fec_clk)

};



int __init mx25_clocks_init(unsigned long fref)

int __init mx25_clocks_init(void)

{

	int i;



	for (i = 0; i < ARRAY_SIZE(lookups); i++)

		clkdev_add(&lookups[i]);



	/* Turn off all clocks except the ones we need to survive, namely:

	 * EMI, GPIO1-3 (CCM_CGCR1[18:16]), GPT1, IOMUXC (CCM_CGCR1[27]), IIM,

	 * SCC

	 */

	__raw_writel((1 << 19), CRM_BASE + CCM_CGCR0);

	__raw_writel((0xf << 16) | (3 << 26), CRM_BASE + CCM_CGCR1);

	__raw_writel((1 << 5), CRM_BASE + CCM_CGCR2);



	mxc_timer_init(&gpt_clk, MX25_IO_ADDRESS(MX25_GPT1_BASE_ADDR), 54);



	return 0;

arch/arm/mach-mx25/mx25pdk.c

+1 −1
Original line number Diff line number Diff line
@@ -91,7 +91,7 @@ static void __init mx25pdk_init(void) 


static void __init mx25pdk_timer_init(void)

{

	mx25_clocks_init(26000000);

	mx25_clocks_init();

}



static struct sys_timer mx25pdk_timer = {