Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 8dd31d74 authored by Alex Deucher's avatar Alex Deucher
Browse files

drm/amdgpu: add support for UVD_NO_OP register 



Writes to this register are the preferred way to do NOPs.

Bump the driver version as well.

Reviewed-by: default avatarChristian König <christian.koenig@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent a22f803c

drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c

+2 −1
Original line number Diff line number Diff line
@@ -54,9 +54,10 @@ 
 *           at the end of IBs.

 * - 3.3.0 - Add VM support for UVD on supported hardware.

 * - 3.4.0 - Add AMDGPU_INFO_NUM_EVICTIONS.

 * - 3.5.0 - Add support for new UVD_NO_OP register.

 */

#define KMS_DRIVER_MAJOR	3

#define KMS_DRIVER_MINOR	4

#define KMS_DRIVER_MINOR	5

#define KMS_DRIVER_PATCHLEVEL	0



int amdgpu_vram_limit = 0;

drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c

+1 −0
Original line number Diff line number Diff line
@@ -818,6 +818,7 @@ static int amdgpu_uvd_cs_reg(struct amdgpu_uvd_cs_ctx *ctx, 
				return r;

			break;

		case mmUVD_ENGINE_CNTL:

		case mmUVD_NO_OP:

			break;

		default:

			DRM_ERROR("Invalid reg 0x%X!\n", reg);

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_2_d.h

+1 −0
Original line number Diff line number Diff line
@@ -34,6 +34,7 @@ 
#define mmUVD_UDEC_ADDR_CONFIG                                                  0x3bd3

#define mmUVD_UDEC_DB_ADDR_CONFIG                                               0x3bd4

#define mmUVD_UDEC_DBW_ADDR_CONFIG                                              0x3bd5

#define mmUVD_NO_OP                                                             0x3bff

#define mmUVD_SEMA_CNTL                                                         0x3d00

#define mmUVD_LMI_EXT40_ADDR                                                    0x3d26

#define mmUVD_CTX_INDEX                                                         0x3d28