Loading drivers/gpu/drm/msm/msm_drv.h +2 −0 Original line number Original line Diff line number Diff line Loading @@ -156,6 +156,8 @@ enum msm_mdp_crtc_property { CRTC_PROP_IDLE_TIMEOUT, CRTC_PROP_IDLE_TIMEOUT, CRTC_PROP_DEST_SCALER, CRTC_PROP_DEST_SCALER, CRTC_PROP_ENABLE_SUI_ENHANCEMENT, /* total # of properties */ /* total # of properties */ CRTC_PROP_COUNT CRTC_PROP_COUNT }; }; Loading drivers/gpu/drm/msm/sde/sde_crtc.c +14 −4 Original line number Original line Diff line number Diff line Loading @@ -1851,7 +1851,8 @@ int sde_crtc_get_secure_transition_ops(struct drm_crtc *crtc, ops |= (SDE_KMS_OPS_WAIT_FOR_TX_DONE | ops |= (SDE_KMS_OPS_WAIT_FOR_TX_DONE | SDE_KMS_OPS_CLEANUP_PLANE_FB); SDE_KMS_OPS_CLEANUP_PLANE_FB); } } if (catalog->sui_misr_supported) if (catalog->sui_misr_supported && sde_crtc->enable_sui_enhancement) smmu_state->sui_misr_state = smmu_state->sui_misr_state = SUI_MISR_ENABLE_REQ; SUI_MISR_ENABLE_REQ; /* secure camera usecase */ /* secure camera usecase */ Loading Loading @@ -1881,7 +1882,8 @@ int sde_crtc_get_secure_transition_ops(struct drm_crtc *crtc, if (old_valid_fb) if (old_valid_fb) ops |= (SDE_KMS_OPS_WAIT_FOR_TX_DONE | ops |= (SDE_KMS_OPS_WAIT_FOR_TX_DONE | SDE_KMS_OPS_CLEANUP_PLANE_FB); SDE_KMS_OPS_CLEANUP_PLANE_FB); if (catalog->sui_misr_supported) if (catalog->sui_misr_supported && sde_crtc->enable_sui_enhancement) smmu_state->sui_misr_state = smmu_state->sui_misr_state = SUI_MISR_DISABLE_REQ; SUI_MISR_DISABLE_REQ; } } Loading Loading @@ -4398,6 +4400,7 @@ static int _sde_crtc_check_secure_state(struct drm_crtc *crtc, return -EINVAL; return -EINVAL; } } sde_crtc = to_sde_crtc(crtc); cstate = to_sde_crtc_state(state); cstate = to_sde_crtc_state(state); secure = sde_crtc_get_property(cstate, CRTC_PROP_SECURITY_LEVEL); secure = sde_crtc_get_property(cstate, CRTC_PROP_SECURITY_LEVEL); Loading Loading @@ -4434,7 +4437,8 @@ static int _sde_crtc_check_secure_state(struct drm_crtc *crtc, } } plane = pstates[i].drm_pstate->plane; plane = pstates[i].drm_pstate->plane; if (!sde_plane_is_sec_ui_allowed(plane)) { if (sde_crtc->enable_sui_enhancement && !sde_plane_is_sec_ui_allowed(plane)) { SDE_ERROR("crtc%d: sec-ui not allowed in p%d\n", SDE_ERROR("crtc%d: sec-ui not allowed in p%d\n", crtc->base.id, plane->base.id); crtc->base.id, plane->base.id); return -EINVAL; return -EINVAL; Loading Loading @@ -4475,7 +4479,6 @@ static int _sde_crtc_check_secure_state(struct drm_crtc *crtc, MSM_DISPLAY_CAP_VID_MODE); MSM_DISPLAY_CAP_VID_MODE); } } sde_crtc = to_sde_crtc(crtc); smmu_state = &sde_kms->smmu_state; smmu_state = &sde_kms->smmu_state; /* /* * In video mode check for null commit before transition * In video mode check for null commit before transition Loading Loading @@ -4987,6 +4990,10 @@ static void sde_crtc_install_properties(struct drm_crtc *crtc, "idle_time", 0, 0, U64_MAX, 0, "idle_time", 0, 0, U64_MAX, 0, CRTC_PROP_IDLE_TIMEOUT); CRTC_PROP_IDLE_TIMEOUT); msm_property_install_range(&sde_crtc->property_info, "enable_sui_enhancement", 0, 0, U64_MAX, 0, CRTC_PROP_ENABLE_SUI_ENHANCEMENT); msm_property_install_blob(&sde_crtc->property_info, "capabilities", msm_property_install_blob(&sde_crtc->property_info, "capabilities", DRM_MODE_PROP_IMMUTABLE, CRTC_PROP_INFO); DRM_MODE_PROP_IMMUTABLE, CRTC_PROP_INFO); Loading Loading @@ -5222,6 +5229,9 @@ static int sde_crtc_atomic_set_property(struct drm_crtc *crtc, cstate->bw_control = true; cstate->bw_control = true; cstate->bw_split_vote = true; cstate->bw_split_vote = true; break; break; case CRTC_PROP_ENABLE_SUI_ENHANCEMENT: sde_crtc->enable_sui_enhancement = val ? true : false; break; case CRTC_PROP_OUTPUT_FENCE: case CRTC_PROP_OUTPUT_FENCE: if (!val) if (!val) goto exit; goto exit; Loading drivers/gpu/drm/msm/sde/sde_crtc.h +20 −0 Original line number Original line Diff line number Diff line Loading @@ -171,6 +171,8 @@ struct sde_crtc_event { * @misr_enable : boolean entry indicates misr enable/disable status. * @misr_enable : boolean entry indicates misr enable/disable status. * @misr_frame_count : misr frame count provided by client * @misr_frame_count : misr frame count provided by client * @misr_data : store misr data before turning off the clocks. * @misr_data : store misr data before turning off the clocks. * @enable_sui_enhancement: indicate enable/disable of sui_enhancement feature * which is set by user-mode. * @sbuf_op_mode_old : inline rotator op mode for previous commit cycle * @sbuf_op_mode_old : inline rotator op mode for previous commit cycle * @sbuf_flush_mask_old: inline rotator flush mask for previous commit * @sbuf_flush_mask_old: inline rotator flush mask for previous commit * @sbuf_flush_mask_all: inline rotator flush mask for all attached planes * @sbuf_flush_mask_all: inline rotator flush mask for all attached planes Loading Loading @@ -242,6 +244,8 @@ struct sde_crtc { u32 misr_frame_count; u32 misr_frame_count; u32 misr_data[CRTC_DUAL_MIXERS]; u32 misr_data[CRTC_DUAL_MIXERS]; bool enable_sui_enhancement; u32 sbuf_op_mode_old; u32 sbuf_op_mode_old; u32 sbuf_flush_mask_old; u32 sbuf_flush_mask_old; u32 sbuf_flush_mask_all; u32 sbuf_flush_mask_all; Loading Loading @@ -689,6 +693,22 @@ static inline int sde_crtc_get_secure_level(struct drm_crtc *crtc, CRTC_PROP_SECURITY_LEVEL); CRTC_PROP_SECURITY_LEVEL); } } /** * sde_crtc_is_sui_enhancement_enabled - Checks if user-mode has enabled the * sui enhancement feature * @crtc: Pointer to crtc */ static inline bool sde_crtc_is_sui_enhancement_enabled(struct drm_crtc *crtc) { struct sde_crtc *sde_crtc; if (!crtc) return false; sde_crtc = to_sde_crtc(crtc); return sde_crtc->enable_sui_enhancement; } /** /** * sde_crtc_get_secure_transition - determines the operations to be * sde_crtc_get_secure_transition - determines the operations to be * performed before transitioning to secure state * performed before transitioning to secure state Loading drivers/gpu/drm/msm/sde/sde_hw_catalog.c +9 −1 Original line number Original line Diff line number Diff line Loading @@ -3245,12 +3245,20 @@ static int _sde_hardware_pre_caps(struct sde_mdss_cfg *sde_cfg, uint32_t hw_rev) sde_cfg->perf.min_prefill_lines = 25; sde_cfg->perf.min_prefill_lines = 25; sde_cfg->vbif_qos_nlvl = 4; sde_cfg->vbif_qos_nlvl = 4; sde_cfg->ts_prefill_rev = 1; sde_cfg->ts_prefill_rev = 1; } else if (IS_SDM845_TARGET(hw_rev) || IS_SDM670_TARGET(hw_rev)) { } else if (IS_SDM845_TARGET(hw_rev)) { /* update sdm845 target here */ /* update sdm845 target here */ sde_cfg->has_wb_ubwc = true; sde_cfg->has_wb_ubwc = true; sde_cfg->perf.min_prefill_lines = 24; sde_cfg->perf.min_prefill_lines = 24; sde_cfg->vbif_qos_nlvl = 8; sde_cfg->vbif_qos_nlvl = 8; sde_cfg->ts_prefill_rev = 2; sde_cfg->ts_prefill_rev = 2; sde_cfg->sui_misr_supported = true; sde_cfg->sui_block_xin_mask = 0x3F71; } else if (IS_SDM670_TARGET(hw_rev)) { /* update sdm670 target here */ sde_cfg->has_wb_ubwc = true; sde_cfg->perf.min_prefill_lines = 24; sde_cfg->vbif_qos_nlvl = 8; sde_cfg->ts_prefill_rev = 2; } else { } else { SDE_ERROR("unsupported chipset id:%X\n", hw_rev); SDE_ERROR("unsupported chipset id:%X\n", hw_rev); sde_cfg->perf.min_prefill_lines = 0xffff; sde_cfg->perf.min_prefill_lines = 0xffff; Loading drivers/gpu/drm/msm/sde/sde_kms.c +26 −0 Original line number Original line Diff line number Diff line Loading @@ -105,6 +105,32 @@ bool sde_is_custom_client(void) return sdecustom; return sdecustom; } } bool sde_kms_is_vbif_operation_allowed(struct sde_kms *sde_kms) { struct drm_device *dev; struct drm_crtc *crtc; bool sui_enhancement = false; if (!sde_kms || !sde_kms->dev) return false; dev = sde_kms->dev; if (!sde_kms->catalog->sui_misr_supported) return true; list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { if (!crtc->state || !crtc->state->active) continue; sui_enhancement |= sde_crtc_is_sui_enhancement_enabled(crtc); } if (!sui_enhancement) return true; return !sde_kms_is_secure_session_inprogress(sde_kms); } #ifdef CONFIG_DEBUG_FS #ifdef CONFIG_DEBUG_FS static int _sde_danger_signal_status(struct seq_file *s, static int _sde_danger_signal_status(struct seq_file *s, bool danger_status) bool danger_status) Loading Loading
drivers/gpu/drm/msm/msm_drv.h +2 −0 Original line number Original line Diff line number Diff line Loading @@ -156,6 +156,8 @@ enum msm_mdp_crtc_property { CRTC_PROP_IDLE_TIMEOUT, CRTC_PROP_IDLE_TIMEOUT, CRTC_PROP_DEST_SCALER, CRTC_PROP_DEST_SCALER, CRTC_PROP_ENABLE_SUI_ENHANCEMENT, /* total # of properties */ /* total # of properties */ CRTC_PROP_COUNT CRTC_PROP_COUNT }; }; Loading
drivers/gpu/drm/msm/sde/sde_crtc.c +14 −4 Original line number Original line Diff line number Diff line Loading @@ -1851,7 +1851,8 @@ int sde_crtc_get_secure_transition_ops(struct drm_crtc *crtc, ops |= (SDE_KMS_OPS_WAIT_FOR_TX_DONE | ops |= (SDE_KMS_OPS_WAIT_FOR_TX_DONE | SDE_KMS_OPS_CLEANUP_PLANE_FB); SDE_KMS_OPS_CLEANUP_PLANE_FB); } } if (catalog->sui_misr_supported) if (catalog->sui_misr_supported && sde_crtc->enable_sui_enhancement) smmu_state->sui_misr_state = smmu_state->sui_misr_state = SUI_MISR_ENABLE_REQ; SUI_MISR_ENABLE_REQ; /* secure camera usecase */ /* secure camera usecase */ Loading Loading @@ -1881,7 +1882,8 @@ int sde_crtc_get_secure_transition_ops(struct drm_crtc *crtc, if (old_valid_fb) if (old_valid_fb) ops |= (SDE_KMS_OPS_WAIT_FOR_TX_DONE | ops |= (SDE_KMS_OPS_WAIT_FOR_TX_DONE | SDE_KMS_OPS_CLEANUP_PLANE_FB); SDE_KMS_OPS_CLEANUP_PLANE_FB); if (catalog->sui_misr_supported) if (catalog->sui_misr_supported && sde_crtc->enable_sui_enhancement) smmu_state->sui_misr_state = smmu_state->sui_misr_state = SUI_MISR_DISABLE_REQ; SUI_MISR_DISABLE_REQ; } } Loading Loading @@ -4398,6 +4400,7 @@ static int _sde_crtc_check_secure_state(struct drm_crtc *crtc, return -EINVAL; return -EINVAL; } } sde_crtc = to_sde_crtc(crtc); cstate = to_sde_crtc_state(state); cstate = to_sde_crtc_state(state); secure = sde_crtc_get_property(cstate, CRTC_PROP_SECURITY_LEVEL); secure = sde_crtc_get_property(cstate, CRTC_PROP_SECURITY_LEVEL); Loading Loading @@ -4434,7 +4437,8 @@ static int _sde_crtc_check_secure_state(struct drm_crtc *crtc, } } plane = pstates[i].drm_pstate->plane; plane = pstates[i].drm_pstate->plane; if (!sde_plane_is_sec_ui_allowed(plane)) { if (sde_crtc->enable_sui_enhancement && !sde_plane_is_sec_ui_allowed(plane)) { SDE_ERROR("crtc%d: sec-ui not allowed in p%d\n", SDE_ERROR("crtc%d: sec-ui not allowed in p%d\n", crtc->base.id, plane->base.id); crtc->base.id, plane->base.id); return -EINVAL; return -EINVAL; Loading Loading @@ -4475,7 +4479,6 @@ static int _sde_crtc_check_secure_state(struct drm_crtc *crtc, MSM_DISPLAY_CAP_VID_MODE); MSM_DISPLAY_CAP_VID_MODE); } } sde_crtc = to_sde_crtc(crtc); smmu_state = &sde_kms->smmu_state; smmu_state = &sde_kms->smmu_state; /* /* * In video mode check for null commit before transition * In video mode check for null commit before transition Loading Loading @@ -4987,6 +4990,10 @@ static void sde_crtc_install_properties(struct drm_crtc *crtc, "idle_time", 0, 0, U64_MAX, 0, "idle_time", 0, 0, U64_MAX, 0, CRTC_PROP_IDLE_TIMEOUT); CRTC_PROP_IDLE_TIMEOUT); msm_property_install_range(&sde_crtc->property_info, "enable_sui_enhancement", 0, 0, U64_MAX, 0, CRTC_PROP_ENABLE_SUI_ENHANCEMENT); msm_property_install_blob(&sde_crtc->property_info, "capabilities", msm_property_install_blob(&sde_crtc->property_info, "capabilities", DRM_MODE_PROP_IMMUTABLE, CRTC_PROP_INFO); DRM_MODE_PROP_IMMUTABLE, CRTC_PROP_INFO); Loading Loading @@ -5222,6 +5229,9 @@ static int sde_crtc_atomic_set_property(struct drm_crtc *crtc, cstate->bw_control = true; cstate->bw_control = true; cstate->bw_split_vote = true; cstate->bw_split_vote = true; break; break; case CRTC_PROP_ENABLE_SUI_ENHANCEMENT: sde_crtc->enable_sui_enhancement = val ? true : false; break; case CRTC_PROP_OUTPUT_FENCE: case CRTC_PROP_OUTPUT_FENCE: if (!val) if (!val) goto exit; goto exit; Loading
drivers/gpu/drm/msm/sde/sde_crtc.h +20 −0 Original line number Original line Diff line number Diff line Loading @@ -171,6 +171,8 @@ struct sde_crtc_event { * @misr_enable : boolean entry indicates misr enable/disable status. * @misr_enable : boolean entry indicates misr enable/disable status. * @misr_frame_count : misr frame count provided by client * @misr_frame_count : misr frame count provided by client * @misr_data : store misr data before turning off the clocks. * @misr_data : store misr data before turning off the clocks. * @enable_sui_enhancement: indicate enable/disable of sui_enhancement feature * which is set by user-mode. * @sbuf_op_mode_old : inline rotator op mode for previous commit cycle * @sbuf_op_mode_old : inline rotator op mode for previous commit cycle * @sbuf_flush_mask_old: inline rotator flush mask for previous commit * @sbuf_flush_mask_old: inline rotator flush mask for previous commit * @sbuf_flush_mask_all: inline rotator flush mask for all attached planes * @sbuf_flush_mask_all: inline rotator flush mask for all attached planes Loading Loading @@ -242,6 +244,8 @@ struct sde_crtc { u32 misr_frame_count; u32 misr_frame_count; u32 misr_data[CRTC_DUAL_MIXERS]; u32 misr_data[CRTC_DUAL_MIXERS]; bool enable_sui_enhancement; u32 sbuf_op_mode_old; u32 sbuf_op_mode_old; u32 sbuf_flush_mask_old; u32 sbuf_flush_mask_old; u32 sbuf_flush_mask_all; u32 sbuf_flush_mask_all; Loading Loading @@ -689,6 +693,22 @@ static inline int sde_crtc_get_secure_level(struct drm_crtc *crtc, CRTC_PROP_SECURITY_LEVEL); CRTC_PROP_SECURITY_LEVEL); } } /** * sde_crtc_is_sui_enhancement_enabled - Checks if user-mode has enabled the * sui enhancement feature * @crtc: Pointer to crtc */ static inline bool sde_crtc_is_sui_enhancement_enabled(struct drm_crtc *crtc) { struct sde_crtc *sde_crtc; if (!crtc) return false; sde_crtc = to_sde_crtc(crtc); return sde_crtc->enable_sui_enhancement; } /** /** * sde_crtc_get_secure_transition - determines the operations to be * sde_crtc_get_secure_transition - determines the operations to be * performed before transitioning to secure state * performed before transitioning to secure state Loading
drivers/gpu/drm/msm/sde/sde_hw_catalog.c +9 −1 Original line number Original line Diff line number Diff line Loading @@ -3245,12 +3245,20 @@ static int _sde_hardware_pre_caps(struct sde_mdss_cfg *sde_cfg, uint32_t hw_rev) sde_cfg->perf.min_prefill_lines = 25; sde_cfg->perf.min_prefill_lines = 25; sde_cfg->vbif_qos_nlvl = 4; sde_cfg->vbif_qos_nlvl = 4; sde_cfg->ts_prefill_rev = 1; sde_cfg->ts_prefill_rev = 1; } else if (IS_SDM845_TARGET(hw_rev) || IS_SDM670_TARGET(hw_rev)) { } else if (IS_SDM845_TARGET(hw_rev)) { /* update sdm845 target here */ /* update sdm845 target here */ sde_cfg->has_wb_ubwc = true; sde_cfg->has_wb_ubwc = true; sde_cfg->perf.min_prefill_lines = 24; sde_cfg->perf.min_prefill_lines = 24; sde_cfg->vbif_qos_nlvl = 8; sde_cfg->vbif_qos_nlvl = 8; sde_cfg->ts_prefill_rev = 2; sde_cfg->ts_prefill_rev = 2; sde_cfg->sui_misr_supported = true; sde_cfg->sui_block_xin_mask = 0x3F71; } else if (IS_SDM670_TARGET(hw_rev)) { /* update sdm670 target here */ sde_cfg->has_wb_ubwc = true; sde_cfg->perf.min_prefill_lines = 24; sde_cfg->vbif_qos_nlvl = 8; sde_cfg->ts_prefill_rev = 2; } else { } else { SDE_ERROR("unsupported chipset id:%X\n", hw_rev); SDE_ERROR("unsupported chipset id:%X\n", hw_rev); sde_cfg->perf.min_prefill_lines = 0xffff; sde_cfg->perf.min_prefill_lines = 0xffff; Loading
drivers/gpu/drm/msm/sde/sde_kms.c +26 −0 Original line number Original line Diff line number Diff line Loading @@ -105,6 +105,32 @@ bool sde_is_custom_client(void) return sdecustom; return sdecustom; } } bool sde_kms_is_vbif_operation_allowed(struct sde_kms *sde_kms) { struct drm_device *dev; struct drm_crtc *crtc; bool sui_enhancement = false; if (!sde_kms || !sde_kms->dev) return false; dev = sde_kms->dev; if (!sde_kms->catalog->sui_misr_supported) return true; list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { if (!crtc->state || !crtc->state->active) continue; sui_enhancement |= sde_crtc_is_sui_enhancement_enabled(crtc); } if (!sui_enhancement) return true; return !sde_kms_is_secure_session_inprogress(sde_kms); } #ifdef CONFIG_DEBUG_FS #ifdef CONFIG_DEBUG_FS static int _sde_danger_signal_status(struct seq_file *s, static int _sde_danger_signal_status(struct seq_file *s, bool danger_status) bool danger_status) Loading