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Commit 8d12e40a authored by Mayank Rana's avatar Mayank Rana
Browse files

ARM: dts: msm: Add USB QMP DP combo PHY device node for SDM845 



This change adds USB QMP DP combo PHY related device node and
required configuration for SDM845.

Change-Id: I60f3dfc52a2bb99a86379c8bfbaf1e8423ff0232
Signed-off-by: default avatarMayank Rana <mrana@codeaurora.org>
parent 4c40cd95

arch/arm64/boot/dts/qcom/sdm845-usb.dtsi

+146 −0
Original line number Diff line number Diff line
@@ -106,6 +106,152 @@ 
		reset-names = "phy_reset";

	};



	/* Primary USB port related QMP USB DP Combo PHY */

	usb_qmp_dp_phy: ssphy@88e8000 {

		compatible = "qcom,usb-ssphy-qmp-dp-combo";

		reg = <0x88e8000 0x3000>;

		reg-names = "qmp_phy_base";



		vdd-supply = <&pm8998_l1>;

		core-supply = <&pm8998_l26>;

		qcom,vdd-voltage-level = <0 880000 880000>;

		qcom,vbus-valid-override;

		qcom,qmp-phy-init-seq =

		/* <reg_offset, value, delay> */

			<0x1048 0x07 0x00 /* COM_PLL_IVCO */

			 0x1080 0x14 0x00 /* COM_SYSCLK_EN_SEL */

			 0x1034 0x08 0x00 /* COM_BIAS_EN_CLKBUFLR_EN */

			 0x1137 0x30 0x00 /* COM_CLK_SELECT */

			 0x103c 0x02 0x00 /* COM_SYS_CLK_CTRL */

			 0x108c 0x08 0x00 /* COM_RESETSM_CNTRL2 */

			 0x115c 0x16 0x00 /* COM_CMN_CONFIG */

			 0x1164 0x01 0x00 /* COM_SVS_MODE_CLK_SEL */

			 0x113c 0x80 0x00 /* COM_HSCLK_SEL */

			 0x10b0 0x82 0x00 /* COM_DEC_START_MODE0 */

			 0x10b8 0xab 0x00 /* COM_DIV_FRAC_START1_MODE0 */

			 0x10bc 0xea 0x00 /* COM_DIV_FRAC_START2_MODE0 */

			 0x10c0 0x02 0x00 /* COM_DIV_FRAC_START3_MODE0 */

			 0x1060 0x06 0x00 /* COM_CP_CTRL_MODE0 */

			 0x1068 0x16 0x00 /* COM_PLL_RCTRL_MODE0 */

			 0x1070 0x36 0x00 /* COM_PLL_CCTRL_MODE0 */

			 0x10dc 0x00 0x00 /* COM_INTEGLOOP_GAIN1_MODE0 */

			 0x10d8 0x3f 0x00 /* COM_INTEGLOOP_GAIN0_MODE0 */

			 0x10f8 0x01 0x00 /* COM_VCO_TUNE2_MODE0 */

			 0x10f4 0xc9 0x00 /* COM_VCO_TUNE1_MODE0 */

			 0x1148 0x0a 0x00 /* COM_CORECLK_DIV_MODE0 */

			 0x10a0 0x00 0x00 /* COM_LOCK_CMP3_MODE0 */

			 0x109c 0x34 0x00 /* COM_LOCK_CMP2_MODE0 */

			 0x1018 0x15 0x00 /* COM_LOCK_CMP1_MODE0 */

			 0x1090 0x04 0x00 /* COM_LOCK_CMP_EN */

			 0x1154 0x00 0x00 /* COM_CORE_CLK_EN */

			 0x1094 0x00 0x00 /* COM_LOCK_CMP_CFG */

			 0x10f0 0x00 0x00 /* COM_VCO_TUNE_MAP */

			 0x1040 0x0a 0x00 /* COM_SYSCLK_BUF_ENABLE */

			 0x1010 0x01 0x00 /* COM_SSC_EN_CENTER */

			 0x101c 0x31 0x00 /* COM_SSC_PER1 */

			 0x1020 0x01 0x00 /* COM_SSC_PER2 */

			 0x1014 0x00 0x00 /* COM_SSC_ADJ_PER1 */

			 0x1018 0x00 0x00 /* COM_SSC_ADJ_PER2 */

			 0x1024 0x85 0x00 /* COM_SSC_STEP_SIZE1 */

			 0x1028 0x07 0x00 /* COM_SSC_STEP_SIZE2 */

			 0x1430 0x0b 0x00 /* RXA_UCDR_FASTLOCK_FO_GAIN */

			 0x14d4 0x0f 0x00 /* RXA_RX_EQU_ADAPTOR_CNTRL2 */

			 0x14d8 0x4e 0x00 /* RXA_RX_EQU_ADAPTOR_CNTRL3 */

			 0x14dc 0x18 0x00 /* RXA_RX_EQU_ADAPTOR_CNTRL4 */

			 0x14f8 0x77 0x00 /* RXA_RX_EQ_OFFSET_ADAPTOR_CNTRL1 */

			 0x14fc 0x80 0x00 /* RXA_RX_OFFSET_ADAPTOR_CNTRL2 */

			 0x1504 0x03 0x00 /* RXA_SIGDET_CNTRL */

			 0x150c 0x16 0x00 /* RXA_SIGDET_DEGLITCH_CNTRL */

			 0x1830 0x0b 0x00 /* RXB_UCDR_FASTLOCK_FO_GAIN */

			 0x18d4 0x0f 0x00 /* RXB_RX_EQU_ADAPTOR_CNTRL2 */

			 0x18d8 0x4e 0x00 /* RXB_RX_EQU_ADAPTOR_CNTRL3 */

			 0x18dc 0x18 0x00 /* RXB_RX_EQU_ADAPTOR_CNTRL4 */

			 0x18f8 0x77 0x00 /* RXB_RX_EQ_OFFSET_ADAPTOR_CNTRL1 */

			 0x18fc 0x80 0x00 /* RXB_RX_OFFSET_ADAPTOR_CNTRL2 */

			 0x1904 0x03 0x00 /* RXB_SIGDET_CNTRL */

			 0x190c 0x16 0x00 /* RXB_SIGDET_DEGLITCH_CNTRL */

			 0x1260 0x10 0x00 /* TXA_HIGHZ_DRVR_EN */

			 0x12a4 0x12 0x00 /* TXA_RCV_DETECT_LVL_2 */

			 0x128c 0x16 0x00 /* TXA_LANE_MODE_1 */

			 0x1648 0x09 0x00 /* TXB_RES_CODE_LANE_OFFSET_RX */

			 0x1644 0x0d 0x00 /* TXB_RES_CODE_LANE_OFFSET_TX */

			 0x1660 0x10 0x00 /* TXB_HIGHZ_DRVR_EN */

			 0x16a4 0x12 0x00 /* TXB_RCV_DETECT_LVL_2 */

			 0x168c 0x16 0x00 /* TXB_LANE_MODE_1 */

			 0x1648 0x09 0x00 /* TXB_RES_CODE_LANE_OFFSET_RX */

			 0x1644 0x0d 0x00 /* TXB_RES_CODE_LANE_OFFSET_TX */

			 0x1cc8 0x83 0x00 /* PCS_FLL_CNTRL2 */

			 0x1ccc 0x09 0x00 /* PCS_FLL_CNT_VAL_L */

			 0x1cd0 0xa2 0x00 /* PCS_FLL_CNT_VAL_H_TOL */

			 0x1cd4 0x40 0x00 /* PCS_FLL_MAN_CODE */

			 0x1cc4 0x02 0x00 /* PCS_FLL_CNTRL1 */

			 0x1c80 0xd1 0x00 /* PCS_LOCK_DETECT_CONFIG1 */

			 0x1c84 0x1f 0x00 /* PCS_LOCK_DETECT_CONFIG2 */

			 0x1c88 0x47 0x00 /* PCS_LOCK_DETECT_CONFIG3 */

			 0x1c64 0x1b 0x00 /* PCS_POWER_STATE_CONFIG2 */

			 0x1434 0x75 0x00 /* RXA_UCDR_SO_SATURATION */

			 0x1834 0x75 0x00 /* RXB_UCDR_SO_SATURATION */

			 0x1dd8 0xba 0x00 /* PCS_RX_SIGDET_LVL */

			 0x1c0c 0x9f 0x00 /* PCS_TXMGN_V0 */

			 0x1c10 0x9f 0x00 /* PCS_TXMGN_V1 */

			 0x1c14 0xb7 0x00 /* PCS_TXMGN_V2 */

			 0x1c18 0x4e 0x00 /* PCS_TXMGN_V3 */

			 0x1c1c 0x65 0x00 /* PCS_TXMGN_V4 */

			 0x1c20 0x6b 0x00 /* PCS_TXMGN_LS */

			 0x1c24 0x15 0x00 /* PCS_TXDEEMPH_M6DB_V0 */

			 0x1c28 0x0d 0x00 /* PCS_TXDEEMPH_M3P5DB_V0 */

			 0x1c2c 0x15 0x00 /* PCS_TXDEEMPH_M6DB_V1 */

			 0x1c30 0x0d 0x00 /* PCS_TXDEEMPH_M3P5DB_V1 */

			 0x1c34 0x15 0x00 /* PCS_TXDEEMPH_M6DB_V2 */

			 0x1c38 0x0d 0x00 /* PCS_TXDEEMPH_M3P5DB_V2 */

			 0x1c3c 0x15 0x00 /* PCS_TXDEEMPH_M6DB_V3 */

			 0x1c40 0x1d 0x00 /* PCS_TXDEEMPH_M3P5DB_V3 */

			 0x1c44 0x15 0x00 /* PCS_TXDEEMPH_M6DB_V4 */

			 0x1c48 0x0d 0x00 /* PCS_TXDEEMPH_M3P5DB_V4 */

			 0x1c4c 0x15 0x00 /* PCS_TXDEEMPH_M6DB_LS */

			 0x1c50 0x0d 0x00 /* PCS_TXDEEMPH_M3P5DB_LS */

			 0x1c5c 0x02 0x00 /* PCS_RATE_SLEW_CNTRL */

			 0x1ca0 0x04 0x00 /* PCS_PWRUP_RESET_DLY_TIME_AUXCLK */

			 0x1c8c 0x44 0x00 /* PCS_TSYNC_RSYNC_TIME */

			 0x1c70 0xe7 0x00 /* PCS_RCVR_DTCT_DLY_P1U2_L */

			 0x1c74 0x03 0x00 /* PCS_RCVR_DTCT_DLY_P1U2_H */

			 0x1c78 0x40 0x00 /* PCS_RCVR_DTCT_DLY_U3_L */

			 0x1c7c 0x00 0x00 /* PCS_RCVR_DTCT_DLY_U3_H */

			 0x1cb8 0x75 0x00 /* PCS_RXEQTRAINING_WAIT_TIME */

			 0x1cb0 0x86 0x00 /* PCS_LFPS_TX_ECSTART_EQTLOCK */

			 0x1cbc 0x13 0x00 /* PCS_RXEQTRAINING_RUN_TIME */

			 0xffffffff 0xffffffff 0x00>;



		qcom,qmp-phy-reg-offset =

				<0x1d74 /* USB3_DP_PCS_PCS_STATUS */

				 0x1cd8 /* USB3_DP_PCS_AUTONOMOUS_MODE_CTRL */

				 0x1cdc /* USB3_DP_PCS_LFPS_RXTERM_IRQ_CLEAR */

				 0x1c04 /* USB3_DP_PCS_POWER_DOWN_CONTROL */

				 0x1c00 /* USB3_DP_PCS_SW_RESET */

				 0x1c08 /* USB3_DP_PCS_START_CONTROL */

				 0x2a18 /* USB3_DP_DP_PHY_PD_CTL */

				 0x0008 /* USB3_DP_COM_POWER_DOWN_CTRL */

				 0x0004 /* USB3_DP_COM_SW_RESET */

				 0x001c /* USB3_DP_COM_RESET_OVRD_CTRL */

				 0x0000 /* USB3_DP_COM_PHY_MODE_CTRL */

				 0x0010 /* USB3_DP_COM_TYPEC_CTRL */

				 0x000c /* USB3_DP_COM_SWI_CTRL */

				 0x1a0c>; /* USB3_DP_PCS_MISC_CLAMP_ENABLE */



		clocks = <&clock_gcc GCC_USB3_PRIM_PHY_AUX_CLK>,

			 <&clock_gcc GCC_USB3_PRIM_PHY_PIPE_CLK>,

			 <&clock_rpmh RPMH_CXO_CLK>,

			 <&clock_gcc GCC_USB3_PRIM_CLKREF_CLK>,

			 <&clock_gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>;



		clock-names = "aux_clk", "pipe_clk", "ref_clk_src",

				"ref_clk", "com_aux_clk";



		resets = <&clock_gcc GCC_USB3_DP_PHY_PRIM_BCR>;

		reset-names = "phy_reset";

		status = "disabled";

	};



	dbm_1p5: dbm@a8f8000 {

		compatible = "qcom,usb-dbm-1p5";

		reg = <0xa8f8000 0x400>;