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Commit 8cfb4e3d authored by Arnd Bergmann's avatar Arnd Bergmann
Browse files

Merge tag 'for-3.17/bcm-dt' of git://github.com/broadcom/mach-bcm into next/dt 

Merge "ARM: mach-bcm: dt updatees for 3.17" from Matt Porter:

- BCM Mobile SMP support
- BRCM STB platform support

* tag 'for-3.17/bcm-dt' of git://github.com/broadcom/mach-bcm

:
  ARM: brcmstb: dts: add a reference DTS for Broadcom 7445
  ARM: brcmstb: gic: add compatible string for Broadcom Brahma15
  ARM: brcmstb: add misc. DT bindings for brcmstb
  ARM: brcmstb: add CPU binding for Broadcom Brahma15
  ARM: dts: enable SMP support for bcm21664
  ARM: dts: enable SMP support for bcm28155
  devicetree: bindings: document Broadcom CPU enable method

Signed-off-by: default avatarArnd Bergmann <arnd@arndb.de>
parents 565f46dc 79187a8e

Documentation/devicetree/bindings/arm/bcm/brcm,bcm11351-cpu-method

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Broadcom Kona Family CPU Enable Method

--------------------------------------

This binding defines the enable method used for starting secondary

CPUs in the following Broadcom SoCs:

  BCM11130, BCM11140, BCM11351, BCM28145, BCM28155, BCM21664



The enable method is specified by defining the following required

properties in the "cpus" device tree node:

  - enable-method = "brcm,bcm11351-cpu-method";

  - secondary-boot-reg = <...>;



The secondary-boot-reg property is a u32 value that specifies the

physical address of the register used to request the ROM holding pen

code release a secondary CPU.  The value written to the register is

formed by encoding the target CPU id into the low bits of the

physical start address it should jump to.



Example:

	cpus {

		#address-cells = <1>;

		#size-cells = <0>;

		enable-method = "brcm,bcm11351-cpu-method";

		secondary-boot-reg = <0x3500417c>;



		cpu0: cpu@0 {

			device_type = "cpu";

			compatible = "arm,cortex-a9";

			reg = <0>;

		};



		cpu1: cpu@1 {

			device_type = "cpu";

			compatible = "arm,cortex-a9";

			reg = <1>;

		};

	};

Documentation/devicetree/bindings/arm/brcm-brcmstb.txt

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ARM Broadcom STB platforms Device Tree Bindings

-----------------------------------------------

Boards with Broadcom Brahma15 ARM-based BCMxxxx (generally BCM7xxx variants)

SoC shall have the following DT organization:



Required root node properties:

    - compatible: "brcm,bcm<chip_id>", "brcm,brcmstb"



example:

/ {

    #address-cells = <2>;

    #size-cells = <2>;

    model = "Broadcom STB (bcm7445)";

    compatible = "brcm,bcm7445", "brcm,brcmstb";



Further, syscon nodes that map platform-specific registers used for general

system control is required:



    - compatible: "brcm,bcm<chip_id>-sun-top-ctrl", "syscon"

    - compatible: "brcm,bcm<chip_id>-hif-cpubiuctrl", "syscon"

    - compatible: "brcm,bcm<chip_id>-hif-continuation", "syscon"



example:

    rdb {

        #address-cells = <1>;

        #size-cells = <1>;

        compatible = "simple-bus";

        ranges = <0 0x00 0xf0000000 0x1000000>;



        sun_top_ctrl: syscon@404000 {

            compatible = "brcm,bcm7445-sun-top-ctrl", "syscon";

            reg = <0x404000 0x51c>;

        };



        hif_cpubiuctrl: syscon@3e2400 {

            compatible = "brcm,bcm7445-hif-cpubiuctrl", "syscon";

            reg = <0x3e2400 0x5b4>;

        };



        hif_continuation: syscon@452000 {

            compatible = "brcm,bcm7445-hif-continuation", "syscon";

            reg = <0x452000 0x100>;

        };

    };



Lastly, nodes that allow for support of SMP initialization and reboot are

required:



smpboot

-------

Required properties:



    - compatible

        The string "brcm,brcmstb-smpboot".



    - syscon-cpu

        A phandle / integer array property which lets the BSP know the location

        of certain CPU power-on registers.



        The layout of the property is as follows:

            o a phandle to the "hif_cpubiuctrl" syscon node

            o offset to the base CPU power zone register

            o offset to the base CPU reset register



    - syscon-cont

        A phandle pointing to the syscon node which describes the CPU boot

        continuation registers.

            o a phandle to the "hif_continuation" syscon node



example:

    smpboot {

        compatible = "brcm,brcmstb-smpboot";

        syscon-cpu = <&hif_cpubiuctrl 0x88 0x178>;

        syscon-cont = <&hif_continuation>;

    };



reboot

-------

Required properties



    - compatible

        The string property "brcm,brcmstb-reboot".



    - syscon

        A phandle / integer array that points to the syscon node which describes

        the general system reset registers.

            o a phandle to "sun_top_ctrl"

            o offset to the "reset source enable" register

            o offset to the "software master reset" register



example:

    reboot {

        compatible = "brcm,brcmstb-reboot";

        syscon = <&sun_top_ctrl 0x304 0x308>;

    };

Documentation/devicetree/bindings/arm/cpus.txt

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@@ -165,6 +165,7 @@ nodes to be present and contain the properties described below. 
			    "arm,cortex-r4"

			    "arm,cortex-r5"

			    "arm,cortex-r7"

			    "brcm,brahma-b15"

			    "faraday,fa526"

			    "intel,sa110"

			    "intel,sa1100"
@@ -186,6 +187,7 @@ nodes to be present and contain the properties described below. 
			  can be one of:

			    "allwinner,sun6i-a31"

			    "arm,psci"

			    "brcm,brahma-b15"

			    "marvell,armada-375-smp"

			    "marvell,armada-380-smp"

			    "marvell,armada-xp-smp"

Documentation/devicetree/bindings/arm/gic.txt

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@@ -16,6 +16,7 @@ Main node required properties: 
	"arm,cortex-a9-gic"

	"arm,cortex-a7-gic"

	"arm,arm11mp-gic"

	"brcm,brahma-b15-gic"

- interrupt-controller : Identifies the node as an interrupt controller

- #interrupt-cells : Specifies the number of cells needed to encode an

  interrupt source.  The type shall be a <u32> and the value shall be 3.

arch/arm/boot/dts/Makefile

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@@ -59,6 +59,8 @@ dtb-$(CONFIG_ARCH_BERLIN) += \ 
	berlin2-sony-nsz-gs7.dtb	\

	berlin2cd-google-chromecast.dtb	\

	berlin2q-marvell-dmp.dtb

dtb-$(CONFIG_ARCH_BRCMSTB) += \

	bcm7445-bcm97445svmb.dtb

dtb-$(CONFIG_ARCH_DAVINCI) += da850-enbw-cmc.dtb \

	da850-evm.dtb

dtb-$(CONFIG_ARCH_EFM32) += efm32gg-dk3750.dtb