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Commit 8ceec332 authored by John Garry's avatar John Garry Committed by Martin K. Petersen
Browse files

hisi_sas: Fix v1 itct masks 



The mask fields are for quad-words, so add ULL suffix.  Also
unreferenced ITCT_HDR_BREAK_REPLY and ITCT_HDR_MAX_BURST are removed.

Fixes: 50af155b ("hisi_sas: Add v1 hardware reg")

Signed-off-by: default avatarJohn Garry <john.garry@huawei.com>
Reviewed-by: default avatarShane Seymour <shane.seymour@hpe.com>
Reviewed-by: default avatarMatthew R. Ochs <mrochs@linux.vnet.ibm.com>
Signed-off-by: default avatarMartin K. Petersen <martin.petersen@oracle.com>
parent d63c7dd5

drivers/scsi/hisi_sas/hisi_sas_v1_hw.c

+12 −17
Original line number Diff line number Diff line
@@ -247,41 +247,36 @@ 
/* ITCT header */

/* qw0 */

#define ITCT_HDR_DEV_TYPE_OFF		0

#define ITCT_HDR_DEV_TYPE_MSK		(0x3 << ITCT_HDR_DEV_TYPE_OFF)

#define ITCT_HDR_DEV_TYPE_MSK		(0x3ULL << ITCT_HDR_DEV_TYPE_OFF)

#define ITCT_HDR_VALID_OFF		2

#define ITCT_HDR_VALID_MSK		(0x1 << ITCT_HDR_VALID_OFF)

#define ITCT_HDR_BREAK_REPLY_ENA_OFF	3

#define ITCT_HDR_BREAK_REPLY_ENA_MSK	(0x1 << ITCT_HDR_BREAK_REPLY_ENA_OFF)

#define ITCT_HDR_VALID_MSK		(0x1ULL << ITCT_HDR_VALID_OFF)

#define ITCT_HDR_AWT_CONTROL_OFF	4

#define ITCT_HDR_AWT_CONTROL_MSK	(0x1 << ITCT_HDR_AWT_CONTROL_OFF)

#define ITCT_HDR_AWT_CONTROL_MSK	(0x1ULL << ITCT_HDR_AWT_CONTROL_OFF)

#define ITCT_HDR_MAX_CONN_RATE_OFF	5

#define ITCT_HDR_MAX_CONN_RATE_MSK	(0xf << ITCT_HDR_MAX_CONN_RATE_OFF)

#define ITCT_HDR_MAX_CONN_RATE_MSK	(0xfULL << ITCT_HDR_MAX_CONN_RATE_OFF)

#define ITCT_HDR_VALID_LINK_NUM_OFF	9

#define ITCT_HDR_VALID_LINK_NUM_MSK	(0xf << ITCT_HDR_VALID_LINK_NUM_OFF)

#define ITCT_HDR_VALID_LINK_NUM_MSK	(0xfULL << ITCT_HDR_VALID_LINK_NUM_OFF)

#define ITCT_HDR_PORT_ID_OFF		13

#define ITCT_HDR_PORT_ID_MSK		(0x7 << ITCT_HDR_PORT_ID_OFF)

#define ITCT_HDR_PORT_ID_MSK		(0x7ULL << ITCT_HDR_PORT_ID_OFF)

#define ITCT_HDR_SMP_TIMEOUT_OFF	16

#define ITCT_HDR_SMP_TIMEOUT_MSK	(0xffff << ITCT_HDR_SMP_TIMEOUT_OFF)

#define ITCT_HDR_MAX_BURST_BYTES_OFF	16

#define ITCT_HDR_MAX_BURST_BYTES_MSK	(0xffffffff << \

					ITCT_MAX_BURST_BYTES_OFF)

#define ITCT_HDR_SMP_TIMEOUT_MSK	(0xffffULL << ITCT_HDR_SMP_TIMEOUT_OFF)

/* qw1 */

#define ITCT_HDR_MAX_SAS_ADDR_OFF	0

#define ITCT_HDR_MAX_SAS_ADDR_MSK	(0xffffffffffffffff << \

					ITCT_HDR_MAX_SAS_ADDR_OFF)

/* qw2 */

#define ITCT_HDR_IT_NEXUS_LOSS_TL_OFF	0

#define ITCT_HDR_IT_NEXUS_LOSS_TL_MSK	(0xffff << \

#define ITCT_HDR_IT_NEXUS_LOSS_TL_MSK	(0xffffULL << \

					ITCT_HDR_IT_NEXUS_LOSS_TL_OFF)

#define ITCT_HDR_BUS_INACTIVE_TL_OFF	16

#define ITCT_HDR_BUS_INACTIVE_TL_MSK	(0xffff << \

#define ITCT_HDR_BUS_INACTIVE_TL_MSK	(0xffffULL << \

					ITCT_HDR_BUS_INACTIVE_TL_OFF)

#define ITCT_HDR_MAX_CONN_TL_OFF	32

#define ITCT_HDR_MAX_CONN_TL_MSK	(0xffff << \

#define ITCT_HDR_MAX_CONN_TL_MSK	(0xffffULL << \

					ITCT_HDR_MAX_CONN_TL_OFF)

#define ITCT_HDR_REJ_OPEN_TL_OFF	48

#define ITCT_HDR_REJ_OPEN_TL_MSK	(0xffff << \

					ITCT_REJ_OPEN_TL_OFF)

#define ITCT_HDR_REJ_OPEN_TL_MSK	(0xffffULL << \

					ITCT_HDR_REJ_OPEN_TL_OFF)



/* Err record header */

#define ERR_HDR_DMA_TX_ERR_TYPE_OFF	0