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Commit 8cd290a0 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge git://git.kernel.org/pub/scm/linux/kernel/git/davem/sparc 

* git://git.kernel.org/pub/scm/linux/kernel/git/davem/sparc:
  sparc: Size mondo queues more sanely.
  sparc: Access kernel TSB using physical addressing when possible.
  sparc: Fix __atomic_add_unless() return value.
  sparc: use kbuild-generic support for true asm-generic header files
  sparc: Use popc when possible for ffs/__ffs/ffz.
  sparc: Set reboot-cmd using reboot data hypervisor call if available.
  sparc: Add some missing hypervisor API groups.
  sparc: Use hweight64() in popc emulation.
  sparc: Use popc if possible for hweight routines.
  sparc: Minor tweaks to Niagara page copy/clear.
  sparc: Sanitize cpu feature detection and reporting.
parents 07d952dc 961f65fc

arch/sparc/include/asm/Kbuild

+5 −0
Original line number Diff line number Diff line
@@ -16,3 +16,8 @@ header-y += traps.h 
header-y += uctx.h

header-y += utrap.h

header-y += watchdog.h



generic-y += div64.h

generic-y += local64.h

generic-y += irq_regs.h

generic-y += local.h

arch/sparc/include/asm/bitops_64.h

+8 −41
Original line number Diff line number Diff line
@@ -26,61 +26,28 @@ extern void change_bit(unsigned long nr, volatile unsigned long *addr); 
#define smp_mb__before_clear_bit()	barrier()

#define smp_mb__after_clear_bit()	barrier()



#include <asm-generic/bitops/ffz.h>

#include <asm-generic/bitops/__ffs.h>

#include <asm-generic/bitops/fls.h>

#include <asm-generic/bitops/__fls.h>

#include <asm-generic/bitops/fls64.h>



#ifdef __KERNEL__



extern int ffs(int x);

extern unsigned long __ffs(unsigned long);



#include <asm-generic/bitops/ffz.h>

#include <asm-generic/bitops/sched.h>

#include <asm-generic/bitops/ffs.h>



/*

 * hweightN: returns the hamming weight (i.e. the number

 * of bits set) of a N-bit word

 */



#ifdef ULTRA_HAS_POPULATION_COUNT



static inline unsigned int __arch_hweight64(unsigned long w)

{

	unsigned int res;



	__asm__ ("popc %1,%0" : "=r" (res) : "r" (w));

	return res;

}



static inline unsigned int __arch_hweight32(unsigned int w)

{

	unsigned int res;



	__asm__ ("popc %1,%0" : "=r" (res) : "r" (w & 0xffffffff));

	return res;

}

extern unsigned long __arch_hweight64(__u64 w);

extern unsigned int __arch_hweight32(unsigned int w);

extern unsigned int __arch_hweight16(unsigned int w);

extern unsigned int __arch_hweight8(unsigned int w);



static inline unsigned int __arch_hweight16(unsigned int w)

{

	unsigned int res;



	__asm__ ("popc %1,%0" : "=r" (res) : "r" (w & 0xffff));

	return res;

}



static inline unsigned int __arch_hweight8(unsigned int w)

{

	unsigned int res;



	__asm__ ("popc %1,%0" : "=r" (res) : "r" (w & 0xff));

	return res;

}



#else



#include <asm-generic/bitops/arch_hweight.h>



#endif

#include <asm-generic/bitops/const_hweight.h>

#include <asm-generic/bitops/lock.h>

#endif /* __KERNEL__ */

arch/sparc/include/asm/div64.h

deleted100644 → 0
+0 −1
Original line number Diff line number Diff line 
#include <asm-generic/div64.h>

arch/sparc/include/asm/elf_64.h

+29 −36
Original line number Diff line number Diff line
@@ -59,15 +59,33 @@ 
#define R_SPARC_6		45



/* Bits present in AT_HWCAP, primarily for Sparc32.  */



#define HWCAP_SPARC_FLUSH       1    /* CPU supports flush instruction. */

#define HWCAP_SPARC_STBAR       2

#define HWCAP_SPARC_SWAP        4

#define HWCAP_SPARC_MULDIV      8

#define HWCAP_SPARC_V9		16

#define HWCAP_SPARC_ULTRA3	32

#define HWCAP_SPARC_BLKINIT	64

#define HWCAP_SPARC_N2		128

#define HWCAP_SPARC_FLUSH       0x00000001

#define HWCAP_SPARC_STBAR       0x00000002

#define HWCAP_SPARC_SWAP        0x00000004

#define HWCAP_SPARC_MULDIV      0x00000008

#define HWCAP_SPARC_V9		0x00000010

#define HWCAP_SPARC_ULTRA3	0x00000020

#define HWCAP_SPARC_BLKINIT	0x00000040

#define HWCAP_SPARC_N2		0x00000080



/* Solaris compatible AT_HWCAP bits. */

#define AV_SPARC_MUL32		0x00000100 /* 32x32 multiply is efficient */

#define AV_SPARC_DIV32		0x00000200 /* 32x32 divide is efficient */

#define AV_SPARC_FSMULD		0x00000400 /* 'fsmuld' is efficient */

#define AV_SPARC_V8PLUS		0x00000800 /* v9 insn available to 32bit */

#define AV_SPARC_POPC		0x00001000 /* 'popc' is efficient */

#define AV_SPARC_VIS		0x00002000 /* VIS insns available */

#define AV_SPARC_VIS2		0x00004000 /* VIS2 insns available */

#define AV_SPARC_ASI_BLK_INIT	0x00008000 /* block init ASIs available */

#define AV_SPARC_FMAF		0x00010000 /* fused multiply-add */

#define AV_SPARC_VIS3		0x00020000 /* VIS3 insns available */

#define AV_SPARC_HPC		0x00040000 /* HPC insns available */

#define AV_SPARC_RANDOM		0x00080000 /* 'random' insn available */

#define AV_SPARC_TRANS		0x00100000 /* transaction insns available */

#define AV_SPARC_FJFMAU		0x00200000 /* unfused multiply-add */

#define AV_SPARC_IMA		0x00400000 /* integer multiply-add */

#define AV_SPARC_ASI_CACHE_SPARING \

				0x00800000 /* cache sparing ASIs available */



#define CORE_DUMP_USE_REGSET
@@ -162,33 +180,8 @@ typedef struct { 
#define ELF_ET_DYN_BASE		0x0000010000000000UL

#define COMPAT_ELF_ET_DYN_BASE	0x0000000070000000UL





/* This yields a mask that user programs can use to figure out what

   instruction set this cpu supports.  */



/* On Ultra, we support all of the v8 capabilities. */

static inline unsigned int sparc64_elf_hwcap(void)

{

	unsigned int cap = (HWCAP_SPARC_FLUSH | HWCAP_SPARC_STBAR |

			    HWCAP_SPARC_SWAP | HWCAP_SPARC_MULDIV |

			    HWCAP_SPARC_V9);



	if (tlb_type == cheetah || tlb_type == cheetah_plus)

		cap |= HWCAP_SPARC_ULTRA3;

	else if (tlb_type == hypervisor) {

		if (sun4v_chip_type == SUN4V_CHIP_NIAGARA1 ||

		    sun4v_chip_type == SUN4V_CHIP_NIAGARA2 ||

		    sun4v_chip_type == SUN4V_CHIP_NIAGARA3)

			cap |= HWCAP_SPARC_BLKINIT;

		if (sun4v_chip_type == SUN4V_CHIP_NIAGARA2 ||

		    sun4v_chip_type == SUN4V_CHIP_NIAGARA3)

			cap |= HWCAP_SPARC_N2;

	}



	return cap;

}



#define ELF_HWCAP	sparc64_elf_hwcap()

extern unsigned long sparc64_elf_hwcap;

#define ELF_HWCAP	sparc64_elf_hwcap



/* This yields a string that ld.so will use to load implementation

   specific libraries for optimization.  This is more specific in

arch/sparc/include/asm/hypervisor.h

+13 −0
Original line number Diff line number Diff line
@@ -2927,6 +2927,13 @@ extern unsigned long sun4v_ncs_request(unsigned long request, 
#define HV_FAST_FIRE_GET_PERFREG	0x120

#define HV_FAST_FIRE_SET_PERFREG	0x121



#define HV_FAST_REBOOT_DATA_SET		0x172



#ifndef __ASSEMBLY__

extern unsigned long sun4v_reboot_data_set(unsigned long ra,

					   unsigned long len);

#endif



/* Function numbers for HV_CORE_TRAP.  */

#define HV_CORE_SET_VER			0x00

#define HV_CORE_PUTCHAR			0x01
@@ -2940,11 +2947,17 @@ extern unsigned long sun4v_ncs_request(unsigned long request, 
#define HV_GRP_CORE			0x0001

#define HV_GRP_INTR			0x0002

#define HV_GRP_SOFT_STATE		0x0003

#define HV_GRP_TM			0x0080

#define HV_GRP_PCI			0x0100

#define HV_GRP_LDOM			0x0101

#define HV_GRP_SVC_CHAN			0x0102

#define HV_GRP_NCS			0x0103

#define HV_GRP_RNG			0x0104

#define HV_GRP_PBOOT			0x0105

#define HV_GRP_TPM			0x0107

#define HV_GRP_SDIO			0x0108

#define HV_GRP_SDIO_ERR			0x0109

#define HV_GRP_REBOOT_DATA		0x0110

#define HV_GRP_NIAG_PERF		0x0200

#define HV_GRP_FIRE_PERF		0x0201

#define HV_GRP_N2_CPU			0x0202