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Commit 8be6e8f3 authored by Peter Zijlstra's avatar Peter Zijlstra Committed by Ingo Molnar
Browse files

perf_counter: Rename L2 to LL cache 



The top (fastest) and last level (biggest) caches are the most
interesting ones, performance wise.

Signed-off-by: default avatarPeter Zijlstra <a.p.zijlstra@chello.nl>
Cc: Mike Galbraith <efault@gmx.de>
Cc: Paul Mackerras <paulus@samba.org>
Cc: Arnaldo Carvalho de Melo <acme@redhat.com>
LKML-Reference: <new-submission>
[ Fixed the Nehalem LL table to LLC Reference/Miss events ]
Signed-off-by: default avatarIngo Molnar <mingo@elte.hu>
parent f4dbfa8f

arch/powerpc/kernel/power4-pmu.c

+1 −1
Original line number Diff line number Diff line
@@ -561,7 +561,7 @@ static int power4_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = { 
		[C(OP_WRITE)] = {	-1,		-1	},

		[C(OP_PREFETCH)] = {	0,		0	},

	},

	[C(L2)] = {		/* 	RESULT_ACCESS	RESULT_MISS */

	[C(LL)] = {		/* 	RESULT_ACCESS	RESULT_MISS */

		[C(OP_READ)] = {	0,		0	},

		[C(OP_WRITE)] = {	0,		0	},

		[C(OP_PREFETCH)] = {	0xc34,		0	},

arch/powerpc/kernel/power5+-pmu.c

+1 −1
Original line number Diff line number Diff line
@@ -632,7 +632,7 @@ static int power5p_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = { 
		[C(OP_WRITE)] = {	-1,		-1		},

		[C(OP_PREFETCH)] = {	0,		0		},

	},

	[C(L2)] = {		/* 	RESULT_ACCESS	RESULT_MISS */

	[C(LL)] = {		/* 	RESULT_ACCESS	RESULT_MISS */

		[C(OP_READ)] = {	0,		0		},

		[C(OP_WRITE)] = {	0,		0		},

		[C(OP_PREFETCH)] = {	0xc50c3,	0		},

arch/powerpc/kernel/power5-pmu.c

+1 −1
Original line number Diff line number Diff line
@@ -574,7 +574,7 @@ static int power5_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = { 
		[C(OP_WRITE)] = {	-1,		-1		},

		[C(OP_PREFETCH)] = {	0,		0		},

	},

	[C(L2)] = {		/* 	RESULT_ACCESS	RESULT_MISS */

	[C(LL)] = {		/* 	RESULT_ACCESS	RESULT_MISS */

		[C(OP_READ)] = {	0,		0x3c309b	},

		[C(OP_WRITE)] = {	0,		0		},

		[C(OP_PREFETCH)] = {	0xc50c3,	0		},

arch/powerpc/kernel/power6-pmu.c

+1 −1
Original line number Diff line number Diff line
@@ -493,7 +493,7 @@ static int power6_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = { 
		[C(OP_WRITE)] = {	-1,		-1		},

		[C(OP_PREFETCH)] = {	0x4008c,	0		},

	},

	[C(L2)] = {		/* 	RESULT_ACCESS	RESULT_MISS */

	[C(LL)] = {		/* 	RESULT_ACCESS	RESULT_MISS */

		[C(OP_READ)] = {	0x150730,	0x250532	},

		[C(OP_WRITE)] = {	0x250432,	0x150432	},

		[C(OP_PREFETCH)] = {	0x810a6,	0		},

arch/powerpc/kernel/power7-pmu.c

+1 −1
Original line number Diff line number Diff line
@@ -320,7 +320,7 @@ static int power7_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = { 
		[C(OP_WRITE)] = {	-1,		-1	},

		[C(OP_PREFETCH)] = {	0x408a,		0	},

	},

	[C(L2)] = {		/* 	RESULT_ACCESS	RESULT_MISS */

	[C(LL)] = {		/* 	RESULT_ACCESS	RESULT_MISS */

		[C(OP_READ)] = {	0x6080,		0x6084	},

		[C(OP_WRITE)] = {	0x6082,		0x6086	},

		[C(OP_PREFETCH)] = {	0,		0	},