Merge tag 'for-linus-20160523' of git://git.infradead.org/linux-mtd

			bootloader) are used for the physical address decoding.

			As this will change in the future, filling correct

			values here is a requirement.

 - interrupt-controller: The GPMC driver implements and interrupt controller for

			the NAND events "fifoevent" and "termcount" plus the

			rising/falling edges on the GPMC_WAIT pins.

			The interrupt number mapping is as follows

			0 - NAND_fifoevent

			1 - NAND_termcount

			2 - GPMC_WAIT0 pin edge

			3 - GPMC_WAIT1 pin edge, and so on.

 - interrupt-cells:	Must be set to 2

 - gpio-controller:	The GPMC driver implements a GPIO controller for the

			GPMC WAIT pins that can be used as general purpose inputs.

			0 maps to GPMC_WAIT0 pin.

 - gpio-cells:		Must be set to 2

Timing properties for child nodes. All are optional and default to 0.

		#address-cells = <2>;

		#size-cells = <1>;

		ranges = <0 0 0x08000000 0x10000000>; /* CS0 @addr 0x8000000, size 0x10000000 */

		interrupt-controller;

		#interrupt-cells = <2>;

		gpio-controller;

		#gpio-cells = <2>;

		/* child nodes go here */

	};

                         brcm,brcmnand-v5.0

                         brcm,brcmnand-v6.0

                         brcm,brcmnand-v6.1

                         brcm,brcmnand-v6.2

                         brcm,brcmnand-v7.0

                         brcm,brcmnand-v7.1

                         brcm,brcmnand

Required properties:

 - reg:		The CS line the peripheral is connected to

 - compatible:	"ti,omap2-nand"

 - reg:		range id (CS number), base offset and length of the

		NAND I/O space

 - interrupt-parent: must point to gpmc node

 - interrupts:	Two interrupt specifiers, one for fifoevent, one for termcount.

Optional properties:

		locating ECC errors for BCHx algorithms. SoC devices which have

		ELM hardware engines should specify this device node in .dtsi

		Using ELM for ECC error correction frees some CPU cycles.

 - rb-gpios:	GPIO specifier for the ready/busy# pin.

For inline partition table parsing (optional):

	gpmc: gpmc@50000000 {

		compatible = "ti,am3352-gpmc";

		ti,hwmods = "gpmc";

		reg = <0x50000000 0x1000000>;

		reg = <0x50000000 0x36c>;

		interrupts = <100>;

		gpmc,num-cs = <8>;

		gpmc,num-waitpins = <2>;

		#address-cells = <2>;

		#size-cells = <1>;

		ranges = <0 0 0x08000000 0x2000>;	/* CS0: NAND */

		ranges = <0 0 0x08000000 0x1000000>;	/* CS0 space, 16MB */

		elm_id = <&elm>;

		interrupt-controller;

		#interrupt-cells = <2>;

		nand@0,0 {

			reg = <0 0 0>; /* CS0, offset 0 */

			compatible = "ti,omap2-nand";

			reg = <0 0 4>;		/* CS0, offset 0, NAND I/O window 4 */

			interrupt-parent = <&gpmc>;

			interrupts = <0 IRQ_TYPE_NONE>, <1 IRQ_TYPE NONE>;

			nand-bus-width = <16>;

			ti,nand-ecc-opt = "bch8";

			ti,nand-xfer-type = "polled";

			rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 */

			gpmc,sync-clk-ps = <0>;

			gpmc,cs-on-ns = <0>;

* MTD generic binding

* NAND chip and NAND controller generic binding

NAND controller/NAND chip representation:

The NAND controller should be represented with its own DT node, and all

NAND chips attached to this controller should be defined as children nodes

of the NAND controller. This representation should be enforced even for

simple controllers supporting only one chip.

Mandatory NAND controller properties:

- #address-cells: depends on your controller. Should at least be 1 to

		  encode the CS line id.

- #size-cells: depends on your controller. Put zero unless you need a

	       mapping between CS lines and dedicated memory regions

Optional NAND controller properties

- ranges: only needed if you need to define a mapping between CS lines and

	  memory regions

Optional NAND chip properties:

- nand-ecc-mode : String, operation mode of the NAND ecc mode.

  Supported values are: "none", "soft", "hw", "hw_syndrome", "hw_oob_first",

  "soft_bch".

		  Supported values are: "none", "soft", "hw", "hw_syndrome",

		  "hw_oob_first".

		  Deprecated values:

		  "soft_bch": use "soft" and nand-ecc-algo instead

- nand-ecc-algo: string, algorithm of NAND ECC.

		 Supported values are: "hamming", "bch".

- nand-bus-width : 8 or 16 bus width if not present 8

- nand-on-flash-bbt: boolean to enable on flash bbt option if not present false

The interpretation of these parameters is implementation-defined, so not all

implementations must support all possible combinations. However, implementations

are encouraged to further specify the value(s) they support.

Example:

	nand-controller {

		#address-cells = <1>;

		#size-cells = <0>;

		/* controller specific properties */

		nand@0 {

			reg = <0>;

			nand-ecc-mode = "soft_bch";

			/* controller specific properties */

		};

	};

	gpmc_nand_res[2].start = gpmc_get_client_irq(GPMC_IRQ_COUNT_EVENT);

	memset(&s, 0, sizeof(struct gpmc_settings));

	if (gpmc_nand_data->of_node)

		gpmc_read_settings_dt(gpmc_nand_data->of_node, &s);

	else

	gpmc_set_legacy(gpmc_nand_data, &s);

	s.device_nand = true;

	if (err < 0)

		goto out_free_cs;

	gpmc_update_nand_reg(&gpmc_nand_data->reg, gpmc_nand_data->cs);

	if (!gpmc_hwecc_bch_capable(gpmc_nand_data->ecc_opt)) {

		pr_err("omap2-nand: Unsupported NAND ECC scheme selected\n");

		err = -EINVAL;