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Commit 8b9a3fde authored by Arnd Bergmann's avatar Arnd Bergmann
Browse files

Merge tag 'arm-soc/for-4.5/devicetree-arm64' of http://github.com/Broadcom/stblinux into next/dt64 

Merge "Broadcom devicetree-arm64 changes for v4.5" from Florian Fainelli:

This pull request contains Broadcom ARM64-based Device Tree changes:

- Anup Patel adds L2 cache, SMMU, syscon-based reboot, PMU v3, iProc RNG200 (HWRNG) and
  NAND flash controller support to the Northstar 2 SoCs

- Ray Jui adds the I2C Device Tree nodes to the Norsthar 2 SoCs

- Jon Mason enables the clock providers on the Norsthar 2 SoCs

* tag 'arm-soc/for-4.5/devicetree-arm64' of http://github.com/Broadcom/stblinux:
  ARM64: dts: enable clock support for Broadcom NS2
  arm64: dts: Add BRCM IPROC NAND DT node for NS2
  arm64: dts: Add I2C nodes for NS2
  arm64: dts: Add IPROC RNG200 DT node for NS2
  arm64: dts: Add ARM PMUv3 DT node in NS2 DT
  arm64: dts: Add syscon based reboot in DT for NS2
  arm64: dts: Add SMMU DT node for NS2
  arm64: dts: Add L2-cache DT node for NS2
parents 3ef6cf00 d8bd64c1

arch/arm64/boot/dts/broadcom/ns2-svk.dts

+22 −4
Original line number Diff line number Diff line
@@ -50,10 +50,28 @@ 
		device_type = "memory";

		reg = <0x000000000 0x80000000 0x00000000 0x40000000>;

	};

};



&i2c0 {

	status = "ok";

};



	soc: soc {

		uart3: serial@66130000 {

&i2c1 {

	status = "ok";

};



&uart3 {

	status = "ok";

};



&nand {

	nandcs@0 {

		compatible = "brcm,nandcs";

		reg = <0>;

		nand-ecc-mode = "hw";

		nand-ecc-strength = <8>;

		nand-ecc-step-size = <512>;

		#address-cells = <1>;

		#size-cells = <1>;

	};

};

arch/arm64/boot/dts/broadcom/ns2.dtsi

+195 −5
Original line number Diff line number Diff line
@@ -31,6 +31,7 @@ 
 */



#include <dt-bindings/interrupt-controller/arm-gic.h>

#include <dt-bindings/clock/bcm-ns2.h>



/memreserve/ 0x84b00000 0x00000008;
@@ -44,36 +45,44 @@ 
		#address-cells = <2>;

		#size-cells = <0>;



		cpu@0 {

		A57_0: cpu@0 {

			device_type = "cpu";

			compatible = "arm,cortex-a57", "arm,armv8";

			reg = <0 0>;

			enable-method = "spin-table";

			cpu-release-addr = <0 0x84b00000>;

			next-level-cache = <&CLUSTER0_L2>;

		};



		cpu@1 {

		A57_1: cpu@1 {

			device_type = "cpu";

			compatible = "arm,cortex-a57", "arm,armv8";

			reg = <0 1>;

			enable-method = "spin-table";

			cpu-release-addr = <0 0x84b00000>;

			next-level-cache = <&CLUSTER0_L2>;

		};



		cpu@2 {

		A57_2: cpu@2 {

			device_type = "cpu";

			compatible = "arm,cortex-a57", "arm,armv8";

			reg = <0 2>;

			enable-method = "spin-table";

			cpu-release-addr = <0 0x84b00000>;

			next-level-cache = <&CLUSTER0_L2>;

		};



		cpu@3 {

		A57_3: cpu@3 {

			device_type = "cpu";

			compatible = "arm,cortex-a57", "arm,armv8";

			reg = <0 3>;

			enable-method = "spin-table";

			cpu-release-addr = <0 0x84b00000>;

			next-level-cache = <&CLUSTER0_L2>;

		};



		CLUSTER0_L2: l2-cache@000 {

			compatible = "cache";

		};

	};
@@ -89,12 +98,154 @@ 
			      IRQ_TYPE_EDGE_RISING)>;

	};



	pmu {

		compatible = "arm,armv8-pmuv3";

		interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;

		interrupt-affinity = <&A57_0>,

				     <&A57_1>,

				     <&A57_2>,

				     <&A57_3>;

	};



	clocks {

		#address-cells = <1>;

		#size-cells = <1>;



		osc: oscillator {

			#clock-cells = <0>;

			compatible = "fixed-clock";

			clock-frequency = <25000000>;

		};



		iprocmed: iprocmed {

			#clock-cells = <0>;

			compatible = "fixed-factor-clock";

			clocks = <&genpll_scr BCM_NS2_GENPLL_SCR_SCR_CLK>;

			clock-div = <2>;

			clock-mult = <1>;

		};



		iprocslow: iprocslow {

			#clock-cells = <0>;

			compatible = "fixed-factor-clock";

			clocks = <&genpll_scr BCM_NS2_GENPLL_SCR_SCR_CLK>;

			clock-div = <4>;

			clock-mult = <1>;

		};

	};



	soc: soc {

		compatible = "simple-bus";

		#address-cells = <1>;

		#size-cells = <1>;

		ranges = <0 0 0 0xffffffff>;



		smmu: mmu@64000000 {

			compatible = "arm,mmu-500";

			reg = <0x64000000 0x40000>;

			#global-interrupts = <2>;

			interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 236 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>;

			mmu-masters;

		};



		lcpll_ddr: lcpll_ddr@6501d058 {

			#clock-cells = <1>;

			compatible = "brcm,ns2-lcpll-ddr";

			reg = <0x6501d058 0x20>,

			      <0x6501c020 0x4>,

			      <0x6501d04c 0x4>;

			clocks = <&osc>;

			clock-output-names = "lcpll_ddr", "pcie_sata_usb",

					     "ddr", "ddr_ch2_unused",

					     "ddr_ch3_unused", "ddr_ch4_unused",

					     "ddr_ch5_unused";

		};



		lcpll_ports: lcpll_ports@6501d078 {

			#clock-cells = <1>;

			compatible = "brcm,ns2-lcpll-ports";

			reg = <0x6501d078 0x20>,

			      <0x6501c020 0x4>,

			      <0x6501d054 0x4>;

			clocks = <&osc>;

			clock-output-names = "lcpll_ports", "wan", "rgmii",

					     "ports_ch2_unused",

					     "ports_ch3_unused",

					     "ports_ch4_unused",

					     "ports_ch5_unused";

		};



		genpll_scr: genpll_scr@6501d098 {

			#clock-cells = <1>;

			compatible = "brcm,ns2-genpll-scr";

			reg = <0x6501d098 0x32>,

			      <0x6501c020 0x4>,

			      <0x6501d044 0x4>;

			clocks = <&osc>;

			clock-output-names = "genpll_scr", "scr", "fs",

					     "audio_ref", "scr_ch3_unused",

					     "scr_ch4_unused", "scr_ch5_unused";

		};



		genpll_sw: genpll_sw@6501d0c4 {

			#clock-cells = <1>;

			compatible = "brcm,ns2-genpll-sw";

			reg = <0x6501d0c4 0x32>,

			      <0x6501c020 0x4>,

			      <0x6501d044 0x4>;

			clocks = <&osc>;

			clock-output-names = "genpll_sw", "rpe", "250", "nic",

					     "chimp", "port", "sdio";

		};



		crmu: crmu@65024000 {

			compatible = "syscon";

			reg = <0x65024000 0x100>;

		};



		reboot@65024000 {

			compatible ="syscon-reboot";

			regmap = <&crmu>;

			offset = <0x90>;

			mask = <0xfffffffd>;

		};



		gic: interrupt-controller@65210000 {

			compatible = "arm,gic-400";

			#interrupt-cells = <3>;
@@ -105,14 +256,53 @@ 
			      <0x65260000 0x1000>;

		};



		i2c0: i2c@66080000 {

			compatible = "brcm,iproc-i2c";

			reg = <0x66080000 0x100>;

			#address-cells = <1>;

			#size-cells = <0>;

			interrupts = <GIC_SPI 394 IRQ_TYPE_NONE>;

			clock-frequency = <100000>;

			status = "disabled";

		};



		i2c1: i2c@660b0000 {

			compatible = "brcm,iproc-i2c";

			reg = <0x660b0000 0x100>;

			#address-cells = <1>;

			#size-cells = <0>;

			interrupts = <GIC_SPI 395 IRQ_TYPE_NONE>;

			clock-frequency = <100000>;

			status = "disabled";

		};



		uart3: serial@66130000 {

			compatible = "snps,dw-apb-uart";

			reg = <0x66130000 0x100>;

			interrupts = <GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH>;

			reg-shift = <2>;

			reg-io-width = <4>;

			clock-frequency = <23961600>;

			clocks = <&osc>;

			status = "disabled";

		};



		hwrng: hwrng@66220000 {

			compatible = "brcm,iproc-rng200";

			reg = <0x66220000 0x28>;

		};



		nand: nand@66460000 {

			compatible = "brcm,nand-iproc", "brcm,brcmnand-v6.1";

			reg = <0x66460000 0x600>,

			      <0x67015408 0x600>,

			      <0x66460f00 0x20>;

			reg-names = "nand", "iproc-idm", "iproc-ext";

			interrupts = <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>;



			#address-cells = <1>;

			#size-cells = <0>;



			brcm,nand-has-wp;

		};

	};

};