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Commit 8b16b3ab authored by Dedy Lansky's avatar Dedy Lansky Committed by Maya Erez
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wil6210: clear PAL_UNIT_ICR part of device reset



When FW starts running it can get D0 to D3 interrupt that is a leftover
from previous system suspend while FW was not running.
As this interrupt is not relevant anymore, clear it part of device reset
procedure.

Change-Id: I213a18fd59a500914ab22f75a72393786188a08e
Signed-off-by: default avatarDedy Lansky <qca_dlansky@qca.qualcomm.com>
Signed-off-by: default avatarMaya Erez <qca_merez@qca.qualcomm.com>
Signed-off-by: default avatarKalle Valo <kvalo@qca.qualcomm.com>
Git-commit: 7086d861753bc0aaa8b6445f657d8e39953e4fcd
Git-repo: git://git.kernel.org/pub/scm/linux/kernel/git/kvalo/ath.git


Signed-off-by: default avatarMaya Erez <merez@codeaurora.org>
parent e674e6d6
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+2 −0
Original line number Diff line number Diff line
@@ -947,6 +947,8 @@ static void wil_pre_fw_config(struct wil6210_priv *wil)
	/* it is W1C, clear by writing back same value */
	wil_s(wil, RGF_CAF_ICR + offsetof(struct RGF_ICR, ICR), 0);
	wil_w(wil, RGF_CAF_ICR + offsetof(struct RGF_ICR, IMV), ~0);
	/* clear PAL_UNIT_ICR (potential D0->D3 leftover) */
	wil_s(wil, RGF_PAL_UNIT_ICR + offsetof(struct RGF_ICR, ICR), 0);

	if (wil->fw_calib_result > 0) {
		__le32 val = cpu_to_le32(wil->fw_calib_result |
+1 −0
Original line number Diff line number Diff line
@@ -272,6 +272,7 @@ struct RGF_ICR {
	#define BIT_DMA_PSEUDO_CAUSE_MISC	BIT(2)

#define RGF_HP_CTRL			(0x88265c)
#define RGF_PAL_UNIT_ICR		(0x88266c) /* struct RGF_ICR */
#define RGF_PCIE_LOS_COUNTER_CTL	(0x882dc4)

/* MAC timer, usec, for packet lifetime */