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Commit 8a1417de authored by Andrew Isaacson's avatar Andrew Isaacson Committed by Ralf Baechle
Browse files

BCM1480 HT support 


    
PCI support code for PLX 7250 PCI-X tunnel on BCM91480B BigSur board.
    
Signed-Off-By: default avatarAndy Isaacson <adi@broadcom.com>
Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
parent dc41f94f

arch/mips/Kconfig

+1 −0
Original line number Diff line number Diff line
@@ -554,6 +554,7 @@ config SIBYTE_BIGSUR 
	select SWAP_IO_SPACE

	select SYS_SUPPORTS_BIG_ENDIAN

	select SYS_SUPPORTS_LITTLE_ENDIAN

	select PCI_DOMAINS



config SIBYTE_SWARM

	bool "Support for Sibyte BCM91250A-SWARM"

arch/mips/pci/Makefile

+1 −1
Original line number Diff line number Diff line
@@ -46,7 +46,7 @@ obj-$(CONFIG_PMC_YOSEMITE) += fixup-yosemite.o ops-titan.o ops-titan-ht.o \ 
obj-$(CONFIG_SGI_IP27)		+= pci-ip27.o

obj-$(CONFIG_SGI_IP32)		+= fixup-ip32.o ops-mace.o pci-ip32.o

obj-$(CONFIG_SIBYTE_SB1250)	+= fixup-sb1250.o pci-sb1250.o

obj-$(CONFIG_SIBYTE_BCM1x80)	+= pci-bcm1480.o

obj-$(CONFIG_SIBYTE_BCM1x80)	+= pci-bcm1480.o pci-bcm1480ht.o

obj-$(CONFIG_SNI_RM200_PCI)	+= fixup-sni.o ops-sni.o

obj-$(CONFIG_TANBAC_TB0219)	+= fixup-tb0219.o

obj-$(CONFIG_TANBAC_TB0226)	+= fixup-tb0226.o

arch/mips/pci/pci-bcm1480.c

+11 −10
Original line number Diff line number Diff line
@@ -56,13 +56,11 @@ 
static void *cfg_space;



#define PCI_BUS_ENABLED	1

#define LDT_BUS_ENABLED	2

#define PCI_DEVICE_MODE	4

#define PCI_DEVICE_MODE	2



static int bcm1480_bus_status = 0;



#define PCI_BRIDGE_DEVICE  0

#define LDT_BRIDGE_DEVICE  1



/*

 * Read/write 32-bit values in config space.
@@ -95,10 +93,13 @@ int pcibios_plat_dev_init(struct pci_dev *dev) 
 */

static int bcm1480_pci_can_access(struct pci_bus *bus, int devfn)

{

	u32 devno;



	if (!(bcm1480_bus_status & (PCI_BUS_ENABLED | PCI_DEVICE_MODE)))

		return 0;



	if (bus->number == 0) {

		devno = PCI_SLOT(devfn);

 		if (bcm1480_bus_status & PCI_DEVICE_MODE)

			return 0;

		else
@@ -175,15 +176,15 @@ struct pci_ops bcm1480_pci_ops = { 


static struct resource bcm1480_mem_resource = {

	.name	= "BCM1480 PCI MEM",

	.start	= 0x40000000UL,

	.end	= 0x5fffffffUL,

	.start	= 0x30000000UL,

	.end	= 0x3fffffffUL,

	.flags	= IORESOURCE_MEM,

};



static struct resource bcm1480_io_resource = {

	.name	= "BCM1480 PCI I/O",

	.start	= 0x00000000UL,

	.end	= 0x01ffffffUL,

	.start	= 0x2c000000UL,

	.end	= 0x2dffffffUL,

	.flags	= IORESOURCE_IO,

};
@@ -207,9 +208,9 @@ static int __init bcm1480_pcibios_init(void) 
	PCIBIOS_MIN_IO = 0x00008000UL;

	PCIBIOS_MIN_MEM = 0x01000000UL;



	/* Set I/O resource limits.  */

	ioport_resource.end = 0x01ffffffUL;	/* 32MB accessible by bcm1480 */

	iomem_resource.end = 0xffffffffUL;	/* no HT support yet */

	/* Set I/O resource limits. - unlimited for now to accomodate HT */

	ioport_resource.end = 0xffffffffUL;

	iomem_resource.end = 0xffffffffUL;



	cfg_space = ioremap(A_BCM1480_PHYS_PCI_CFG_MATCH_BITS, 16*1024*1024);

arch/mips/pci/pci-bcm1480ht.c

0 → 100644
+224 −0
Original line number Diff line number Diff line 
/*

 * Copyright (C) 2001,2002,2005 Broadcom Corporation

 * Copyright (C) 2004 by Ralf Baechle (ralf@linux-mips.org)

 *

 * This program is free software; you can redistribute it and/or

 * modify it under the terms of the GNU General Public License

 * as published by the Free Software Foundation; either version 2

 * of the License, or (at your option) any later version.

 *

 * This program is distributed in the hope that it will be useful,

 * but WITHOUT ANY WARRANTY; without even the implied warranty of

 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

 * GNU General Public License for more details.

 *

 * You should have received a copy of the GNU General Public License

 * along with this program; if not, write to the Free Software

 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.

 */



/*

 * BCM1480/1455-specific HT support (looking like PCI)

 *

 * This module provides the glue between Linux's PCI subsystem

 * and the hardware.  We basically provide glue for accessing

 * configuration space, and set up the translation for I/O

 * space accesses.

 *

 * To access configuration space, we use ioremap.  In the 32-bit

 * kernel, this consumes either 4 or 8 page table pages, and 16MB of

 * kernel mapped memory.  Hopefully neither of these should be a huge

 * problem.

 *

 */

#include <linux/config.h>

#include <linux/types.h>

#include <linux/pci.h>

#include <linux/kernel.h>

#include <linux/init.h>

#include <linux/mm.h>

#include <linux/console.h>

#include <linux/tty.h>



#include <asm/sibyte/bcm1480_regs.h>

#include <asm/sibyte/bcm1480_scd.h>

#include <asm/sibyte/board.h>

#include <asm/io.h>



/*

 * Macros for calculating offsets into config space given a device

 * structure or dev/fun/reg

 */

#define CFGOFFSET(bus,devfn,where) (((bus)<<16)+((devfn)<<8)+(where))

#define CFGADDR(bus,devfn,where)   CFGOFFSET((bus)->number,(devfn),where)



static void *ht_cfg_space;



#define PCI_BUS_ENABLED	1

#define PCI_DEVICE_MODE	2



static int bcm1480ht_bus_status = 0;



#define PCI_BRIDGE_DEVICE  0

#define HT_BRIDGE_DEVICE   1



/*

 * HT's level-sensitive interrupts require EOI, which is generated

 * through a 4MB memory-mapped region

 */

unsigned long ht_eoi_space;



/*

 * Read/write 32-bit values in config space.

 */

static inline u32 READCFG32(u32 addr)

{

	return *(u32 *)(ht_cfg_space + (addr&~3));

}



static inline void WRITECFG32(u32 addr, u32 data)

{

	*(u32 *)(ht_cfg_space + (addr & ~3)) = data;

}



/*

 * Some checks before doing config cycles:

 * In PCI Device Mode, hide everything on bus 0 except the LDT host

 * bridge.  Otherwise, access is controlled by bridge MasterEn bits.

 */

static int bcm1480ht_can_access(struct pci_bus *bus, int devfn)

{

	u32 devno;



	if (!(bcm1480ht_bus_status & (PCI_BUS_ENABLED | PCI_DEVICE_MODE)))

		return 0;



	if (bus->number == 0) {

		devno = PCI_SLOT(devfn);

 		if (bcm1480ht_bus_status & PCI_DEVICE_MODE)

			return 0;

	}

	return 1;

}



/*

 * Read/write access functions for various sizes of values

 * in config space.  Return all 1's for disallowed accesses

 * for a kludgy but adequate simulation of master aborts.

 */



static int bcm1480ht_pcibios_read(struct pci_bus *bus, unsigned int devfn,

				  int where, int size, u32 * val)

{

	u32 data = 0;



	if ((size == 2) && (where & 1))

		return PCIBIOS_BAD_REGISTER_NUMBER;

	else if ((size == 4) && (where & 3))

		return PCIBIOS_BAD_REGISTER_NUMBER;



	if (bcm1480ht_can_access(bus, devfn))

		data = READCFG32(CFGADDR(bus, devfn, where));

	else

		data = 0xFFFFFFFF;



	if (size == 1)

		*val = (data >> ((where & 3) << 3)) & 0xff;

	else if (size == 2)

		*val = (data >> ((where & 3) << 3)) & 0xffff;

	else

		*val = data;



	return PCIBIOS_SUCCESSFUL;

}



static int bcm1480ht_pcibios_write(struct pci_bus *bus, unsigned int devfn,

				   int where, int size, u32 val)

{

	u32 cfgaddr = CFGADDR(bus, devfn, where);

	u32 data = 0;



	if ((size == 2) && (where & 1))

		return PCIBIOS_BAD_REGISTER_NUMBER;

	else if ((size == 4) && (where & 3))

		return PCIBIOS_BAD_REGISTER_NUMBER;



	if (!bcm1480ht_can_access(bus, devfn))

		return PCIBIOS_BAD_REGISTER_NUMBER;



	data = READCFG32(cfgaddr);



	if (size == 1)

		data = (data & ~(0xff << ((where & 3) << 3))) |

		    (val << ((where & 3) << 3));

	else if (size == 2)

		data = (data & ~(0xffff << ((where & 3) << 3))) |

		    (val << ((where & 3) << 3));

	else

		data = val;



	WRITECFG32(cfgaddr, data);



	return PCIBIOS_SUCCESSFUL;

}



static int bcm1480ht_pcibios_get_busno(void)

{

	return 0;

}



struct pci_ops bcm1480ht_pci_ops = {

	.read	= bcm1480ht_pcibios_read,

	.write	= bcm1480ht_pcibios_write,

};



static struct resource bcm1480ht_mem_resource = {

	.name	= "BCM1480 HT MEM",

	.start	= 0x40000000UL,

	.end	= 0x5fffffffUL,

	.flags	= IORESOURCE_MEM,

};



static struct resource bcm1480ht_io_resource = {

	.name	= "BCM1480 HT I/O",

	.start	= 0x00000000UL,

	.end	= 0x01ffffffUL,

	.flags	= IORESOURCE_IO,

};



struct pci_controller bcm1480ht_controller = {

	.pci_ops	= &bcm1480ht_pci_ops,

	.mem_resource	= &bcm1480ht_mem_resource,

	.io_resource	= &bcm1480ht_io_resource,

	.index		= 1,

	.get_busno	= bcm1480ht_pcibios_get_busno,

};



static int __init bcm1480ht_pcibios_init(void)

{

	uint32_t cmdreg;



	ht_cfg_space = ioremap(A_BCM1480_PHYS_HT_CFG_MATCH_BITS, 16*1024*1024);



	/*

	 * See if the PCI bus has been configured by the firmware.

	 */

	cmdreg = READCFG32(CFGOFFSET(0, PCI_DEVFN(PCI_BRIDGE_DEVICE, 0),

				     PCI_COMMAND));

	if (!(cmdreg & PCI_COMMAND_MASTER)) {

		printk("HT: Skipping HT probe. Bus is not initialized.\n");

		iounmap(ht_cfg_space);

		return 1; /* XXX */

	}

	bcm1480ht_bus_status |= PCI_BUS_ENABLED;



	ht_eoi_space = (unsigned long)

		ioremap(A_BCM1480_PHYS_HT_SPECIAL_MATCH_BYTES,

			4 * 1024 * 1024);



	register_pci_controller(&bcm1480ht_controller);



	return 0;

}



arch_initcall(bcm1480ht_pcibios_init);

arch/mips/pci/pci.c

+11 −6
Original line number Diff line number Diff line
@@ -127,9 +127,13 @@ static int __init pcibios_init(void) 
		if (!hose->iommu)

			PCI_DMA_BUS_IS_PHYS = 1;



		if (hose->get_busno && pci_probe_only)

			next_busno = (*hose->get_busno)();



		bus = pci_scan_bus(next_busno, hose->pci_ops, hose);

		hose->bus = bus;

		hose->need_domain_info = need_domain_info;

		if (bus) {

			next_busno = bus->subordinate + 1;

			/* Don't allow 8-bit bus number overflow inside the hose -

			   reserve some space for bridges. */
@@ -137,6 +141,7 @@ static int __init pcibios_init(void) 
				next_busno = 0;

				need_domain_info = 1;

			}

		}

		continue;



out_free_mem_resource: