Merge ath-next from ath.git

* Qualcomm Atheros ath10k wireless devices

For ath10k devices the calibration data can be provided through Device

Tree. The node is a child node of the PCI controller.

Required properties:

-compatible : Should be "qcom,ath10k"

- compatible: Should be one of the following:

	* "qcom,ath10k"

	* "qcom,ipq4019-wifi"

PCI based devices uses compatible string "qcom,ath10k" and takes only

calibration data via "qcom,ath10k-calibration-data". Rest of the properties

are not applicable for PCI based devices.

AHB based devices (i.e. ipq4019) uses compatible string "qcom,ipq4019-wifi"

and also uses most of the properties defined in this doc.

Optional properties:

- reg: Address and length of the register set for the device.

- resets: Must contain an entry for each entry in reset-names.

          See ../reset/reseti.txt for details.

- reset-names: Must include the list of following reset names,

	       "wifi_cpu_init"

	       "wifi_radio_srif"

	       "wifi_radio_warm"

	       "wifi_radio_cold"

	       "wifi_core_warm"

	       "wifi_core_cold"

- clocks: List of clock specifiers, must contain an entry for each required

          entry in clock-names.

- clock-names: Should contain the clock names "wifi_wcss_cmd", "wifi_wcss_ref",

               "wifi_wcss_rtc".

- interrupts: List of interrupt lines. Must contain an entry

	      for each entry in the interrupt-names property.

- interrupt-names: Must include the entries for MSI interrupt

		   names ("msi0" to "msi15") and legacy interrupt

		   name ("legacy"),

- qcom,msi_addr: MSI interrupt address.

- qcom,msi_base: Base value to add before writing MSI data into

		MSI address register.

- qcom,ath10k-calibration-data : calibration data as an array, the

				 length can vary between hw versions

Example (to supply the calibration data alone):

Example:

In this example, the node is defined as child node of the PCI controller.

pci {

	pcie@0 {

		};

	};

};

Example (to supply ipq4019 SoC wifi block details):

wifi0: wifi@a000000 {

	compatible = "qcom,ipq4019-wifi";

	reg = <0xa000000 0x200000>;

	resets = <&gcc WIFI0_CPU_INIT_RESET>,

		 <&gcc WIFI0_RADIO_SRIF_RESET>,

		 <&gcc WIFI0_RADIO_WARM_RESET>,

		 <&gcc WIFI0_RADIO_COLD_RESET>,

		 <&gcc WIFI0_CORE_WARM_RESET>,

		 <&gcc WIFI0_CORE_COLD_RESET>;

	reset-names = "wifi_cpu_init",

		      "wifi_radio_srif",

		      "wifi_radio_warm",

		      "wifi_radio_cold",

		      "wifi_core_warm",

		      "wifi_core_cold";

	clocks = <&gcc GCC_WCSS2G_CLK>,

		 <&gcc GCC_WCSS2G_REF_CLK>,

		 <&gcc GCC_WCSS2G_RTC_CLK>;

	clock-names = "wifi_wcss_cmd",

		      "wifi_wcss_ref",

		      "wifi_wcss_rtc";

	interrupts = <0 0x20 0x1>,

		     <0 0x21 0x1>,

		     <0 0x22 0x1>,

		     <0 0x23 0x1>,

		     <0 0x24 0x1>,

		     <0 0x25 0x1>,

		     <0 0x26 0x1>,

		     <0 0x27 0x1>,

		     <0 0x28 0x1>,

		     <0 0x29 0x1>,

		     <0 0x2a 0x1>,

		     <0 0x2b 0x1>,

		     <0 0x2c 0x1>,

		     <0 0x2d 0x1>,

		     <0 0x2e 0x1>,

		     <0 0x2f 0x1>,

		     <0 0xa8 0x0>;

	interrupt-names = "msi0",  "msi1",  "msi2",  "msi3",

			  "msi4",  "msi5",  "msi6",  "msi7",

			  "msi8",  "msi9",  "msi10", "msi11",

			  "msi12", "msi13", "msi14", "msi15",

			  "legacy";

	qcom,msi_addr = <0x0b006040>;

	qcom,msi_base = <0x40>;

	qcom,ath10k-calibration-data = [ 01 02 03 ... ];

};

	---help---

	  This module adds support for PCIE bus

config ATH10K_AHB

	bool "Atheros ath10k AHB support"

	depends on ATH10K_PCI && OF && RESET_CONTROLLER

	---help---

	  This module adds support for AHB bus

config ATH10K_DEBUG

	bool "Atheros ath10k debugging"

	depends on ATH10K

ath10k_pci-y += pci.o \

		ce.o

ath10k_pci-$(CONFIG_ATH10K_AHB) += ahb.o

# for tracing framework to find trace.h

CFLAGS_trace.o := -I$(src)

/*

 * Copyright (c) 2016 Qualcomm Atheros, Inc. All rights reserved.

 * Copyright (c) 2015 The Linux Foundation. All rights reserved.

 *

 * Permission to use, copy, modify, and/or distribute this software for any

 * purpose with or without fee is hereby granted, provided that the above

 * copyright notice and this permission notice appear in all copies.

 *

 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES

 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF

 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR

 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES

 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN

 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF

 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.

 */

#ifndef _AHB_H_

#define _AHB_H_

#include <linux/platform_device.h>

struct ath10k_ahb {

	struct platform_device *pdev;

	void __iomem *mem;

	unsigned long mem_len;

	void __iomem *gcc_mem;

	void __iomem *tcsr_mem;

	int irq;

	struct clk *cmd_clk;

	struct clk *ref_clk;

	struct clk *rtc_clk;

	struct reset_control *core_cold_rst;

	struct reset_control *radio_cold_rst;

	struct reset_control *radio_warm_rst;

	struct reset_control *radio_srif_rst;

	struct reset_control *cpu_init_rst;

};

#ifdef CONFIG_ATH10K_AHB

#define ATH10K_GCC_REG_BASE                  0x1800000

#define ATH10K_GCC_REG_SIZE                  0x60000

#define ATH10K_TCSR_REG_BASE                 0x1900000

#define ATH10K_TCSR_REG_SIZE                 0x80000

#define ATH10K_AHB_GCC_FEPLL_PLL_DIV         0x2f020

#define ATH10K_AHB_WIFI_SCRATCH_5_REG        0x4f014

#define ATH10K_AHB_WLAN_CORE_ID_REG          0x82030

#define ATH10K_AHB_TCSR_WIFI0_GLB_CFG        0x49000

#define ATH10K_AHB_TCSR_WIFI1_GLB_CFG        0x49004

#define TCSR_WIFIX_GLB_CFG_DISABLE_CORE_CLK  BIT(25)

#define ATH10K_AHB_TCSR_WCSS0_HALTREQ        0x52000

#define ATH10K_AHB_TCSR_WCSS1_HALTREQ        0x52010

#define ATH10K_AHB_TCSR_WCSS0_HALTACK        0x52004

#define ATH10K_AHB_TCSR_WCSS1_HALTACK        0x52014

#define ATH10K_AHB_AXI_BUS_HALT_TIMEOUT      10 /* msec */

#define AHB_AXI_BUS_HALT_REQ                 1

#define AHB_AXI_BUS_HALT_ACK                 1

#define ATH10K_AHB_CORE_CTRL_CPU_INTR_MASK   1

int ath10k_ahb_init(void);

void ath10k_ahb_exit(void);

#else /* CONFIG_ATH10K_AHB */

static inline int ath10k_ahb_init(void)

{

	return 0;

}

static inline void ath10k_ahb_exit(void)

{

}

#endif /* CONFIG_ATH10K_AHB */

#endif /* _AHB_H_ */