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Commit 88cefb6c authored by Daniel Vetter's avatar Daniel Vetter
Browse files

drm/i915: extract ironlake_fdi_pll_disable 



Simply to make the ilk+ crtc disable path clearer and more symmetric
with the enable function.

Also switch to intel_crtc for the enable function.

Reviewed-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
Signed-Off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent 5d985ac8

drivers/gpu/drm/i915/intel_display.c

+33 −24
Original line number Diff line number Diff line
@@ -2709,11 +2709,10 @@ static void ivb_manual_fdi_link_train(struct drm_crtc *crtc) 
	DRM_DEBUG_KMS("FDI train done.\n");

}



static void ironlake_fdi_pll_enable(struct drm_crtc *crtc)

static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)

{

	struct drm_device *dev = crtc->dev;

	struct drm_device *dev = intel_crtc->base.dev;

	struct drm_i915_private *dev_priv = dev->dev_private;

	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);

	int pipe = intel_crtc->pipe;

	u32 reg, temp;
@@ -2754,6 +2753,35 @@ static void ironlake_fdi_pll_enable(struct drm_crtc *crtc) 
	}

}



static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)

{

	struct drm_device *dev = intel_crtc->base.dev;

	struct drm_i915_private *dev_priv = dev->dev_private;

	int pipe = intel_crtc->pipe;

	u32 reg, temp;



	/* Switch from PCDclk to Rawclk */

	reg = FDI_RX_CTL(pipe);

	temp = I915_READ(reg);

	I915_WRITE(reg, temp & ~FDI_PCDCLK);



	/* Disable CPU FDI TX PLL */

	reg = FDI_TX_CTL(pipe);

	temp = I915_READ(reg);

	I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);



	POSTING_READ(reg);

	udelay(100);



	reg = FDI_RX_CTL(pipe);

	temp = I915_READ(reg);

	I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);



	/* Wait for the clocks to turn off. */

	POSTING_READ(reg);

	udelay(100);

}



static void cpt_phase_pointer_disable(struct drm_device *dev, int pipe)

{

	struct drm_i915_private *dev_priv = dev->dev_private;
@@ -3201,7 +3229,7 @@ static void ironlake_crtc_enable(struct drm_crtc *crtc) 
	is_pch_port = intel_crtc_driving_pch(crtc);



	if (is_pch_port)

		ironlake_fdi_pll_enable(crtc);

		ironlake_fdi_pll_enable(intel_crtc);

	else

		ironlake_fdi_disable(crtc);
@@ -3304,26 +3332,7 @@ static void ironlake_crtc_disable(struct drm_crtc *crtc) 
	/* disable PCH DPLL */

	intel_disable_pch_pll(intel_crtc);



	/* Switch from PCDclk to Rawclk */

	reg = FDI_RX_CTL(pipe);

	temp = I915_READ(reg);

	I915_WRITE(reg, temp & ~FDI_PCDCLK);



	/* Disable CPU FDI TX PLL */

	reg = FDI_TX_CTL(pipe);

	temp = I915_READ(reg);

	I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);



	POSTING_READ(reg);

	udelay(100);



	reg = FDI_RX_CTL(pipe);

	temp = I915_READ(reg);

	I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);



	/* Wait for the clocks to turn off. */

	POSTING_READ(reg);

	udelay(100);

	ironlake_fdi_pll_disable(intel_crtc);



	intel_crtc->active = false;

	intel_update_watermarks(dev);