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Commit 889fa782 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'drm-intel-fixes-2014-08-08' of git://anongit.freedesktop.org/drm-intel 

Pull intel drm fixes from Daniel Vetter:
 "So I heard that proper pull requests have a revert on top ;-) So here
  we go with my usual mid-merge-window pile of fixes.

[ Ed. This revert thing had better not become the "in" thing ]

   Big fix is the duct-tape for ring init on g4x platforms, we seem to
  have found the magic again to make those machines as happy as before
  (not perfect though unfortunately, but that was never the case).

  Otherwise fixes all over:
   - tune down some overzealous debug output
   - VDD power sequencing fix after resume
   - bunch of dsi fixes for baytrail among them hw state checker
     de-noising
   - bunch of error state capture fixes for bdw
   - misc tiny fixes/workarounds for various platforms

  Last minute rebase was to kick out two patches that shouldn't have
  been in here - they're for the state checker, so 0 functional code
  affected.

  Jani's back from vacation, so he'll take over -fixes from here"

* tag 'drm-intel-fixes-2014-08-08' of git://anongit.freedesktop.org/drm-intel: (21 commits)
  Revert "drm/i915: Enable semaphores on BDW"
  drm/i915: read HEAD register back in init_ring_common() to enforce ordering
  drm/i915: Fix crash when failing to parse MIPI VBT
  drm/i915: Bring GPU Freq to min while suspending.
  drm/i915: Fix DEIER and GTIER collecting for BDW.
  drm/i915: Don't accumulate hangcheck score on forward progress
  drm/i915: Add the WaCsStallBeforeStateCacheInvalidate:bdw workaround.
  drm/i915: Refactor Broadwell PIPE_CONTROL emission into a helper.
  drm/i915: Fix threshold for choosing 32 vs. 64 precisions for VLV DDL values
  drm/i915: Fix drain latency precision multipler for VLV
  drm/i915: Collect gtier properly on HSW.
  drm/i915: Tune down MCH_SSKPD values warning
  drm/i915: Tune done rc6 enabling output
  drm/i915: Don't require dev->struct_mutex in psr_match_conditions
  drm/i915: Fix error state collecting
  drm/i915: fix VDD state tracking after system resume
  drm/i915: Add correct hw/sw config check for DSI encoder
  drm/i915: factor out intel_edp_panel_vdd_sanitize
  drm/i915: wait for all DSI FIFOs to be empty
  drm/i915: work around warning in i915_gem_gtt
  ...
parents a7d7a143 be71eabe

drivers/gpu/drm/i915/i915_drv.c

+4 −0
Original line number Diff line number Diff line
@@ -481,6 +481,10 @@ bool i915_semaphore_is_enabled(struct drm_device *dev) 
	if (i915.semaphores >= 0)

		return i915.semaphores;



	/* Until we get further testing... */

	if (IS_GEN8(dev))

		return false;



#ifdef CONFIG_INTEL_IOMMU

	/* Enable semaphores on SNB when IO remapping is off */

	if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped)

drivers/gpu/drm/i915/i915_drv.h

+2 −1
Original line number Diff line number Diff line
@@ -53,7 +53,7 @@ 


#define DRIVER_NAME		"i915"

#define DRIVER_DESC		"Intel Graphics"

#define DRIVER_DATE		"20140620"

#define DRIVER_DATE		"20140725"



enum pipe {

	INVALID_PIPE = -1,
@@ -314,6 +314,7 @@ struct drm_i915_error_state { 
	u32 eir;

	u32 pgtbl_er;

	u32 ier;

	u32 gtier[4];

	u32 ccid;

	u32 derrmr;

	u32 forcewake;

drivers/gpu/drm/i915/i915_gem.c

+1 −1
Original line number Diff line number Diff line
@@ -4545,7 +4545,7 @@ i915_gem_suspend(struct drm_device *dev) 


	del_timer_sync(&dev_priv->gpu_error.hangcheck_timer);

	cancel_delayed_work_sync(&dev_priv->mm.retire_work);

	cancel_delayed_work_sync(&dev_priv->mm.idle_work);

	flush_delayed_work(&dev_priv->mm.idle_work);



	return 0;

drivers/gpu/drm/i915/i915_gem_gtt.c

+6 −5
Original line number Diff line number Diff line
@@ -1415,7 +1415,7 @@ static void gen8_ggtt_insert_entries(struct i915_address_space *vm, 
		(gen8_gtt_pte_t __iomem *)dev_priv->gtt.gsm + first_entry;

	int i = 0;

	struct sg_page_iter sg_iter;

	dma_addr_t addr = 0;

	dma_addr_t addr = 0; /* shut up gcc */



	for_each_sg_page(st->sgl, &sg_iter, st->nents, 0) {

		addr = sg_dma_address(sg_iter.sg) +
@@ -1461,7 +1461,7 @@ static void gen6_ggtt_insert_entries(struct i915_address_space *vm, 
		(gen6_gtt_pte_t __iomem *)dev_priv->gtt.gsm + first_entry;

	int i = 0;

	struct sg_page_iter sg_iter;

	dma_addr_t addr;

	dma_addr_t addr = 0;



	for_each_sg_page(st->sgl, &sg_iter, st->nents, 0) {

		addr = sg_page_iter_dma_address(&sg_iter);
@@ -1475,9 +1475,10 @@ static void gen6_ggtt_insert_entries(struct i915_address_space *vm, 
	 * of NUMA access patterns. Therefore, even with the way we assume

	 * hardware should work, we must keep this posting read for paranoia.

	 */

	if (i != 0)

		WARN_ON(readl(&gtt_entries[i-1]) !=

			vm->pte_encode(addr, level, true, flags));

	if (i != 0) {

		unsigned long gtt = readl(&gtt_entries[i-1]);

		WARN_ON(gtt != vm->pte_encode(addr, level, true, flags));

	}



	/* This next bit makes the above posting read even more important. We

	 * want to flush the TLBs only after we're certain all the PTE updates

drivers/gpu/drm/i915/i915_gpu_error.c

+24 −11
Original line number Diff line number Diff line
@@ -229,6 +229,8 @@ static const char *hangcheck_action_to_str(enum intel_ring_hangcheck_action a) 
		return "wait";

	case HANGCHECK_ACTIVE:

		return "active";

	case HANGCHECK_ACTIVE_LOOP:

		return "active (loop)";

	case HANGCHECK_KICK:

		return "kick";

	case HANGCHECK_HUNG:
@@ -359,6 +361,12 @@ int i915_error_state_to_str(struct drm_i915_error_state_buf *m, 
	err_printf(m, "PCI ID: 0x%04x\n", dev->pdev->device);

	err_printf(m, "EIR: 0x%08x\n", error->eir);

	err_printf(m, "IER: 0x%08x\n", error->ier);

	if (INTEL_INFO(dev)->gen >= 8) {

		for (i = 0; i < 4; i++)

			err_printf(m, "GTIER gt %d: 0x%08x\n", i,

				   error->gtier[i]);

	} else if (HAS_PCH_SPLIT(dev) || IS_VALLEYVIEW(dev))

		err_printf(m, "GTIER: 0x%08x\n", error->gtier[0]);

	err_printf(m, "PGTBL_ER: 0x%08x\n", error->pgtbl_er);

	err_printf(m, "FORCEWAKE: 0x%08x\n", error->forcewake);

	err_printf(m, "DERRMR: 0x%08x\n", error->derrmr);
@@ -784,7 +792,8 @@ static void gen8_record_semaphore_state(struct drm_i915_private *dev_priv, 
		if (ring == to)

			continue;



		signal_offset = (GEN8_SIGNAL_OFFSET(ring, i) & PAGE_MASK) / 4;

		signal_offset = (GEN8_SIGNAL_OFFSET(ring, i) & (PAGE_SIZE - 1))

				/ 4;

		tmp = error->semaphore_obj->pages[0];

		idx = intel_ring_sync_index(ring, to);
@@ -1091,6 +1100,7 @@ static void i915_capture_reg_state(struct drm_i915_private *dev_priv, 
				   struct drm_i915_error_state *error)

{

	struct drm_device *dev = dev_priv->dev;

	int i;



	/* General organization

	 * 1. Registers specific to a single generation
@@ -1102,7 +1112,8 @@ static void i915_capture_reg_state(struct drm_i915_private *dev_priv, 


	/* 1: Registers specific to a single generation */

	if (IS_VALLEYVIEW(dev)) {

		error->ier = I915_READ(GTIER) | I915_READ(VLV_IER);

		error->gtier[0] = I915_READ(GTIER);

		error->ier = I915_READ(VLV_IER);

		error->forcewake = I915_READ(FORCEWAKE_VLV);

	}
@@ -1135,16 +1146,18 @@ static void i915_capture_reg_state(struct drm_i915_private *dev_priv, 
	if (HAS_HW_CONTEXTS(dev))

		error->ccid = I915_READ(CCID);



	if (HAS_PCH_SPLIT(dev))

		error->ier = I915_READ(DEIER) | I915_READ(GTIER);

	else {

		if (IS_GEN2(dev))

	if (INTEL_INFO(dev)->gen >= 8) {

		error->ier = I915_READ(GEN8_DE_MISC_IER);

		for (i = 0; i < 4; i++)

			error->gtier[i] = I915_READ(GEN8_GT_IER(i));

	} else if (HAS_PCH_SPLIT(dev)) {

		error->ier = I915_READ(DEIER);

		error->gtier[0] = I915_READ(GTIER);

	} else if (IS_GEN2(dev)) {

		error->ier = I915_READ16(IER);

		else

	} else if (!IS_VALLEYVIEW(dev)) {

		error->ier = I915_READ(IER);

	}



	/* 4: Everything else */

	error->eir = I915_READ(EIR);

	error->pgtbl_er = I915_READ(PGTBL_ER);