Merge "clk: qcom: clk-alpha-pll: Check for the parent rate during round_rate" into msm-4.9 (883a65a4) · Commits · e / devices / android_kernel_fairphone_FP3

drivers/clk/qcom/clk-alpha-pll.c

+9 −0

Original line number	Diff line number	Diff line
		@@ -307,6 +307,15 @@ alpha_pll_round_rate(const struct clk_alpha_pll *pll, unsigned long rate,
		u64 quotient;
		int alpha_bw = ALPHA_BITWIDTH;

		/*
		* The PLLs parent rate is zero probably since the parent hasn't
		* registered yet. Return early with the requested rate.
		*/
		if (!prate) {
		pr_debug("PLLs parent rate hasn't been initialized.\n");
		return rate;
		}

		quotient = rate;
		remainder = do_div(quotient, prate);
		*l = quotient;