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Commit 87b89e85 authored by navin patidar's avatar navin patidar Committed by Greg Kroah-Hartman
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staging: rtl8188eu: Rework function odm_RX_HWAntDivInit() 



Rename CamelCase function name.
Remove unnecessary comments.

Signed-off-by: default avatarnavin patidar <navin.patidar@gmail.com>
Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@linuxfoundation.org>
parent 146b9010

drivers/staging/rtl8188eu/hal/odm_RTL8188E.c

+16 −15
Original line number Diff line number Diff line
@@ -21,34 +21,35 @@ 
#include "odm_precomp.h"

#include "phy.h"



static void odm_RX_HWAntDivInit(struct odm_dm_struct *dm_odm)

static void dm_rx_hw_antena_div_init(struct odm_dm_struct *dm_odm)

{

	struct adapter *adapter = dm_odm->Adapter;

	u32 value32;



	if (*(dm_odm->mp_mode) == 1) {

		dm_odm->AntDivType = CGCS_RX_SW_ANTDIV;

		phy_set_bb_reg(adapter, ODM_REG_IGI_A_11N, BIT7, 0); /*  disable HW AntDiv */

		phy_set_bb_reg(adapter, ODM_REG_LNA_SWITCH_11N, BIT31, 1);  /*  1:CG, 0:CS */

		phy_set_bb_reg(adapter, ODM_REG_IGI_A_11N, BIT7, 0);

		phy_set_bb_reg(adapter, ODM_REG_LNA_SWITCH_11N, BIT31, 1);

		return;

	}

	ODM_RT_TRACE(dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("odm_RX_HWAntDivInit()\n"));



	/* MAC Setting */

	value32 = phy_query_bb_reg(adapter, ODM_REG_ANTSEL_PIN_11N, bMaskDWord);

	phy_set_bb_reg(adapter, ODM_REG_ANTSEL_PIN_11N, bMaskDWord, value32|(BIT23|BIT25)); /* Reg4C[25]=1, Reg4C[23]=1 for pin output */

	phy_set_bb_reg(adapter, ODM_REG_ANTSEL_PIN_11N, bMaskDWord,

		       value32|(BIT23|BIT25));

	/* Pin Settings */

	phy_set_bb_reg(adapter, ODM_REG_PIN_CTRL_11N, BIT9|BIT8, 0);/* Reg870[8]=1'b0, Reg870[9]=1'b0	antsel antselb by HW */

	phy_set_bb_reg(adapter, ODM_REG_RX_ANT_CTRL_11N, BIT10, 0);	/* Reg864[10]=1'b0	antsel2 by HW */

	phy_set_bb_reg(adapter, ODM_REG_LNA_SWITCH_11N, BIT22, 1);	/* Regb2c[22]=1'b0	disable CS/CG switch */

	phy_set_bb_reg(adapter, ODM_REG_LNA_SWITCH_11N, BIT31, 1);	/* Regb2c[31]=1'b1	output at CG only */

	phy_set_bb_reg(adapter, ODM_REG_PIN_CTRL_11N, BIT9|BIT8, 0);

	phy_set_bb_reg(adapter, ODM_REG_RX_ANT_CTRL_11N, BIT10, 0);

	phy_set_bb_reg(adapter, ODM_REG_LNA_SWITCH_11N, BIT22, 1);

	phy_set_bb_reg(adapter, ODM_REG_LNA_SWITCH_11N, BIT31, 1);

	/* OFDM Settings */

	phy_set_bb_reg(adapter, ODM_REG_ANTDIV_PARA1_11N, bMaskDWord, 0x000000a0);

	phy_set_bb_reg(adapter, ODM_REG_ANTDIV_PARA1_11N, bMaskDWord,

		       0x000000a0);

	/* CCK Settings */

	phy_set_bb_reg(adapter, ODM_REG_BB_PWR_SAV4_11N, BIT7, 1); /* Fix CCK PHY status report issue */

	phy_set_bb_reg(adapter, ODM_REG_CCK_ANTDIV_PARA2_11N, BIT4, 1); /* CCK complete HW AntDiv within 64 samples */

	phy_set_bb_reg(adapter, ODM_REG_BB_PWR_SAV4_11N, BIT7, 1);

	phy_set_bb_reg(adapter, ODM_REG_CCK_ANTDIV_PARA2_11N, BIT4, 1);

	ODM_UpdateRxIdleAnt_88E(dm_odm, MAIN_ANT);

	phy_set_bb_reg(adapter, ODM_REG_ANT_MAPPING1_11N, 0xFFFF, 0x0201);	/* antenna mapping table */

	phy_set_bb_reg(adapter, ODM_REG_ANT_MAPPING1_11N, 0xFFFF, 0x0201);

}



static void odm_TRX_HWAntDivInit(struct odm_dm_struct *dm_odm)
@@ -177,7 +178,7 @@ void ODM_AntennaDiversityInit_88E(struct odm_dm_struct *dm_odm) 
	ODM_RT_TRACE(dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("dm_odm->bIsMPChip=%s\n", (dm_odm->bIsMPChip ? "true" : "false")));



	if (dm_odm->AntDivType == CGCS_RX_HW_ANTDIV)

		odm_RX_HWAntDivInit(dm_odm);

		dm_rx_hw_antena_div_init(dm_odm);

	else if (dm_odm->AntDivType == CG_TRX_HW_ANTDIV)

		odm_TRX_HWAntDivInit(dm_odm);

	else if (dm_odm->AntDivType == CG_TRX_SMART_ANTDIV)