Loading Makefile +1 −1 Original line number Diff line number Diff line VERSION = 4 PATCHLEVEL = 9 SUBLEVEL = 56 SUBLEVEL = 58 EXTRAVERSION = NAME = Roaring Lionus Loading arch/mips/include/asm/irq.h +1 −1 Original line number Diff line number Diff line Loading @@ -18,7 +18,7 @@ #include <irq.h> #define IRQ_STACK_SIZE THREAD_SIZE #define IRQ_STACK_START (IRQ_STACK_SIZE - sizeof(unsigned long)) #define IRQ_STACK_START (IRQ_STACK_SIZE - 16) extern void *irq_stack[NR_CPUS]; Loading arch/mips/math-emu/cp1emu.c +0 −2 Original line number Diff line number Diff line Loading @@ -2386,7 +2386,6 @@ static int fpu_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx, break; default: /* Reserved R6 ops */ pr_err("Reserved MIPS R6 CMP.condn.S operation\n"); return SIGILL; } } Loading Loading @@ -2460,7 +2459,6 @@ static int fpu_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx, break; default: /* Reserved R6 ops */ pr_err("Reserved MIPS R6 CMP.condn.D operation\n"); return SIGILL; } } Loading arch/powerpc/perf/isa207-common.h +4 −0 Original line number Diff line number Diff line Loading @@ -201,6 +201,10 @@ CNST_PMC_VAL(1) | CNST_PMC_VAL(2) | CNST_PMC_VAL(3) | \ CNST_PMC_VAL(4) | CNST_PMC_VAL(5) | CNST_PMC_VAL(6) | CNST_NC_VAL /* * Lets restrict use of PMC5 for instruction counting. */ #define P9_DD1_TEST_ADDER (ISA207_TEST_ADDER | CNST_PMC_VAL(5)) /* Bits in MMCR1 for PowerISA v2.07 */ #define MMCR1_UNIT_SHIFT(pmc) (60 - (4 * ((pmc) - 1))) Loading arch/powerpc/perf/power9-pmu.c +1 −1 Original line number Diff line number Diff line Loading @@ -295,7 +295,7 @@ static struct power_pmu power9_pmu = { .name = "POWER9", .n_counter = MAX_PMU_COUNTERS, .add_fields = ISA207_ADD_FIELDS, .test_adder = ISA207_TEST_ADDER, .test_adder = P9_DD1_TEST_ADDER, .compute_mmcr = isa207_compute_mmcr, .config_bhrb = power9_config_bhrb, .bhrb_filter_map = power9_bhrb_filter_map, Loading Loading
Makefile +1 −1 Original line number Diff line number Diff line VERSION = 4 PATCHLEVEL = 9 SUBLEVEL = 56 SUBLEVEL = 58 EXTRAVERSION = NAME = Roaring Lionus Loading
arch/mips/include/asm/irq.h +1 −1 Original line number Diff line number Diff line Loading @@ -18,7 +18,7 @@ #include <irq.h> #define IRQ_STACK_SIZE THREAD_SIZE #define IRQ_STACK_START (IRQ_STACK_SIZE - sizeof(unsigned long)) #define IRQ_STACK_START (IRQ_STACK_SIZE - 16) extern void *irq_stack[NR_CPUS]; Loading
arch/mips/math-emu/cp1emu.c +0 −2 Original line number Diff line number Diff line Loading @@ -2386,7 +2386,6 @@ static int fpu_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx, break; default: /* Reserved R6 ops */ pr_err("Reserved MIPS R6 CMP.condn.S operation\n"); return SIGILL; } } Loading Loading @@ -2460,7 +2459,6 @@ static int fpu_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx, break; default: /* Reserved R6 ops */ pr_err("Reserved MIPS R6 CMP.condn.D operation\n"); return SIGILL; } } Loading
arch/powerpc/perf/isa207-common.h +4 −0 Original line number Diff line number Diff line Loading @@ -201,6 +201,10 @@ CNST_PMC_VAL(1) | CNST_PMC_VAL(2) | CNST_PMC_VAL(3) | \ CNST_PMC_VAL(4) | CNST_PMC_VAL(5) | CNST_PMC_VAL(6) | CNST_NC_VAL /* * Lets restrict use of PMC5 for instruction counting. */ #define P9_DD1_TEST_ADDER (ISA207_TEST_ADDER | CNST_PMC_VAL(5)) /* Bits in MMCR1 for PowerISA v2.07 */ #define MMCR1_UNIT_SHIFT(pmc) (60 - (4 * ((pmc) - 1))) Loading
arch/powerpc/perf/power9-pmu.c +1 −1 Original line number Diff line number Diff line Loading @@ -295,7 +295,7 @@ static struct power_pmu power9_pmu = { .name = "POWER9", .n_counter = MAX_PMU_COUNTERS, .add_fields = ISA207_ADD_FIELDS, .test_adder = ISA207_TEST_ADDER, .test_adder = P9_DD1_TEST_ADDER, .compute_mmcr = isa207_compute_mmcr, .config_bhrb = power9_config_bhrb, .bhrb_filter_map = power9_bhrb_filter_map, Loading