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Commit 875d90b2 authored by Viswanadha Raju Thotakura's avatar Viswanadha Raju Thotakura Committed by Soundrapandian Jeyaprakash
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msm: camera: Add memory barrier for CSIPHY registers 



Add memory barrier to sequence the register writes.

Change-Id: Ide80d61b2626cace2ff4c541fe8fb33dea378c13
Signed-off-by: default avatarViswanadha Raju Thotakura <viswanad@codeaurora.org>
Signed-off-by: default avatarSoundrapandian Jeyaprakash <jsoundra@codeaurora.org>
parent cdd957e9
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