Loading drivers/iommu/arm-smmu.c +0 −61 Original line number Diff line number Diff line Loading @@ -3192,65 +3192,6 @@ static void arm_smmu_trigger_fault(struct iommu_domain *domain, arm_smmu_power_off(smmu->pwr); } static unsigned long arm_smmu_reg_read(struct iommu_domain *domain, unsigned long offset) { struct arm_smmu_domain *smmu_domain = to_smmu_domain(domain); struct arm_smmu_device *smmu; struct arm_smmu_cfg *cfg = &smmu_domain->cfg; void __iomem *cb_base; unsigned long val; if (offset >= SZ_4K) { pr_err("Invalid offset: 0x%lx\n", offset); return 0; } smmu = smmu_domain->smmu; if (!smmu) { WARN(1, "Can't read registers of a detached domain\n"); val = 0; return val; } if (arm_smmu_power_on(smmu->pwr)) return 0; cb_base = ARM_SMMU_CB_BASE(smmu) + ARM_SMMU_CB(smmu, cfg->cbndx); val = readl_relaxed(cb_base + offset); arm_smmu_power_off(smmu->pwr); return val; } static void arm_smmu_reg_write(struct iommu_domain *domain, unsigned long offset, unsigned long val) { struct arm_smmu_domain *smmu_domain = to_smmu_domain(domain); struct arm_smmu_device *smmu; struct arm_smmu_cfg *cfg = &smmu_domain->cfg; void __iomem *cb_base; if (offset >= SZ_4K) { pr_err("Invalid offset: 0x%lx\n", offset); return; } smmu = smmu_domain->smmu; if (!smmu) { WARN(1, "Can't read registers of a detached domain\n"); return; } if (arm_smmu_power_on(smmu->pwr)) return; cb_base = ARM_SMMU_CB_BASE(smmu) + ARM_SMMU_CB(smmu, cfg->cbndx); writel_relaxed(val, cb_base + offset); arm_smmu_power_off(smmu->pwr); } static void arm_smmu_tlbi_domain(struct iommu_domain *domain) { struct arm_smmu_domain *smmu_domain = to_smmu_domain(domain); Loading Loading @@ -3292,8 +3233,6 @@ static struct iommu_ops arm_smmu_ops = { .of_xlate = arm_smmu_of_xlate, .pgsize_bitmap = -1UL, /* Restricted during device attach */ .trigger_fault = arm_smmu_trigger_fault, .reg_read = arm_smmu_reg_read, .reg_write = arm_smmu_reg_write, .tlbi_domain = arm_smmu_tlbi_domain, .enable_config_clocks = arm_smmu_enable_config_clocks, .disable_config_clocks = arm_smmu_disable_config_clocks, Loading drivers/iommu/iommu.c +0 −24 Original line number Diff line number Diff line Loading @@ -1677,30 +1677,6 @@ void iommu_trigger_fault(struct iommu_domain *domain, unsigned long flags) domain->ops->trigger_fault(domain, flags); } /** * iommu_reg_read() - read an IOMMU register * * Reads the IOMMU register at the given offset. */ unsigned long iommu_reg_read(struct iommu_domain *domain, unsigned long offset) { if (domain->ops->reg_read) return domain->ops->reg_read(domain, offset); return 0; } /** * iommu_reg_write() - write an IOMMU register * * Writes the given value to the IOMMU register at the given offset. */ void iommu_reg_write(struct iommu_domain *domain, unsigned long offset, unsigned long val) { if (domain->ops->reg_write) domain->ops->reg_write(domain, offset, val); } void iommu_get_dm_regions(struct device *dev, struct list_head *list) { const struct iommu_ops *ops = dev->bus->iommu_ops; Loading include/linux/iommu.h +0 −4 Original line number Diff line number Diff line Loading @@ -244,10 +244,6 @@ struct iommu_ops { /* Get the number of windows per domain */ u32 (*domain_get_windows)(struct iommu_domain *domain); void (*trigger_fault)(struct iommu_domain *domain, unsigned long flags); unsigned long (*reg_read)(struct iommu_domain *domain, unsigned long offset); void (*reg_write)(struct iommu_domain *domain, unsigned long val, unsigned long offset); void (*tlbi_domain)(struct iommu_domain *domain); int (*enable_config_clocks)(struct iommu_domain *domain); void (*disable_config_clocks)(struct iommu_domain *domain); Loading Loading
drivers/iommu/arm-smmu.c +0 −61 Original line number Diff line number Diff line Loading @@ -3192,65 +3192,6 @@ static void arm_smmu_trigger_fault(struct iommu_domain *domain, arm_smmu_power_off(smmu->pwr); } static unsigned long arm_smmu_reg_read(struct iommu_domain *domain, unsigned long offset) { struct arm_smmu_domain *smmu_domain = to_smmu_domain(domain); struct arm_smmu_device *smmu; struct arm_smmu_cfg *cfg = &smmu_domain->cfg; void __iomem *cb_base; unsigned long val; if (offset >= SZ_4K) { pr_err("Invalid offset: 0x%lx\n", offset); return 0; } smmu = smmu_domain->smmu; if (!smmu) { WARN(1, "Can't read registers of a detached domain\n"); val = 0; return val; } if (arm_smmu_power_on(smmu->pwr)) return 0; cb_base = ARM_SMMU_CB_BASE(smmu) + ARM_SMMU_CB(smmu, cfg->cbndx); val = readl_relaxed(cb_base + offset); arm_smmu_power_off(smmu->pwr); return val; } static void arm_smmu_reg_write(struct iommu_domain *domain, unsigned long offset, unsigned long val) { struct arm_smmu_domain *smmu_domain = to_smmu_domain(domain); struct arm_smmu_device *smmu; struct arm_smmu_cfg *cfg = &smmu_domain->cfg; void __iomem *cb_base; if (offset >= SZ_4K) { pr_err("Invalid offset: 0x%lx\n", offset); return; } smmu = smmu_domain->smmu; if (!smmu) { WARN(1, "Can't read registers of a detached domain\n"); return; } if (arm_smmu_power_on(smmu->pwr)) return; cb_base = ARM_SMMU_CB_BASE(smmu) + ARM_SMMU_CB(smmu, cfg->cbndx); writel_relaxed(val, cb_base + offset); arm_smmu_power_off(smmu->pwr); } static void arm_smmu_tlbi_domain(struct iommu_domain *domain) { struct arm_smmu_domain *smmu_domain = to_smmu_domain(domain); Loading Loading @@ -3292,8 +3233,6 @@ static struct iommu_ops arm_smmu_ops = { .of_xlate = arm_smmu_of_xlate, .pgsize_bitmap = -1UL, /* Restricted during device attach */ .trigger_fault = arm_smmu_trigger_fault, .reg_read = arm_smmu_reg_read, .reg_write = arm_smmu_reg_write, .tlbi_domain = arm_smmu_tlbi_domain, .enable_config_clocks = arm_smmu_enable_config_clocks, .disable_config_clocks = arm_smmu_disable_config_clocks, Loading
drivers/iommu/iommu.c +0 −24 Original line number Diff line number Diff line Loading @@ -1677,30 +1677,6 @@ void iommu_trigger_fault(struct iommu_domain *domain, unsigned long flags) domain->ops->trigger_fault(domain, flags); } /** * iommu_reg_read() - read an IOMMU register * * Reads the IOMMU register at the given offset. */ unsigned long iommu_reg_read(struct iommu_domain *domain, unsigned long offset) { if (domain->ops->reg_read) return domain->ops->reg_read(domain, offset); return 0; } /** * iommu_reg_write() - write an IOMMU register * * Writes the given value to the IOMMU register at the given offset. */ void iommu_reg_write(struct iommu_domain *domain, unsigned long offset, unsigned long val) { if (domain->ops->reg_write) domain->ops->reg_write(domain, offset, val); } void iommu_get_dm_regions(struct device *dev, struct list_head *list) { const struct iommu_ops *ops = dev->bus->iommu_ops; Loading
include/linux/iommu.h +0 −4 Original line number Diff line number Diff line Loading @@ -244,10 +244,6 @@ struct iommu_ops { /* Get the number of windows per domain */ u32 (*domain_get_windows)(struct iommu_domain *domain); void (*trigger_fault)(struct iommu_domain *domain, unsigned long flags); unsigned long (*reg_read)(struct iommu_domain *domain, unsigned long offset); void (*reg_write)(struct iommu_domain *domain, unsigned long val, unsigned long offset); void (*tlbi_domain)(struct iommu_domain *domain); int (*enable_config_clocks)(struct iommu_domain *domain); void (*disable_config_clocks)(struct iommu_domain *domain); Loading