Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 8714918e authored by Kyle Piefer's avatar Kyle Piefer
Browse files

msm: kgsl: Update PDC code to use TCS 1 and 3 



When using the new RSCC sleep sequence, TCS 1
and 3 are used instead of 0 and 1. Update the PDC
programming to match this so the wrong TCS is not
used.

CRs-Fixed: 2120475
Change-Id: Ib4df3a239cebf2b6701ea105a4d34cb66bb045dc
Signed-off-by: default avatarKyle Piefer <kpiefer@codeaurora.org>
parent a7bbb875

drivers/gpu/msm/a6xx_reg.h

+12 −0
Original line number Original line Diff line number Diff line
@@ -1004,6 +1004,18 @@ 
#define PDC_GPU_TCS1_CMD0_MSGID			0x21575

#define PDC_GPU_TCS1_CMD0_MSGID			0x21575

#define PDC_GPU_TCS1_CMD0_ADDR			0x21576

#define PDC_GPU_TCS1_CMD0_ADDR			0x21576

#define PDC_GPU_TCS1_CMD0_DATA			0x21577

#define PDC_GPU_TCS1_CMD0_DATA			0x21577

#define PDC_GPU_TCS2_CONTROL			0x215A4

#define PDC_GPU_TCS2_CMD_ENABLE_BANK		0x215A5

#define PDC_GPU_TCS2_CMD_WAIT_FOR_CMPL_BANK	0x215A6

#define PDC_GPU_TCS2_CMD0_MSGID			0x215A7

#define PDC_GPU_TCS2_CMD0_ADDR			0x215A8

#define PDC_GPU_TCS2_CMD0_DATA			0x215A9

#define PDC_GPU_TCS3_CONTROL			0x215D6

#define PDC_GPU_TCS3_CMD_ENABLE_BANK		0x215D7

#define PDC_GPU_TCS3_CMD_WAIT_FOR_CMPL_BANK	0x215D8

#define PDC_GPU_TCS3_CMD0_MSGID			0x215D9

#define PDC_GPU_TCS3_CMD0_ADDR			0x215DA

#define PDC_GPU_TCS3_CMD0_DATA			0x215DB

#define PDC_GPU_SEQ_MEM_0			0xA0000

#define PDC_GPU_SEQ_MEM_0			0xA0000





#endif /* _A6XX_REG_H */

#endif /* _A6XX_REG_H */

drivers/gpu/msm/adreno_a6xx.c

+21 −21
Original line number Original line Diff line number Diff line
@@ -937,42 +937,42 @@ static void _load_gmu_rpmh_ucode(struct kgsl_device *device) 
	_regwrite(gmu->pdc_reg_virt, PDC_GPU_SEQ_MEM_0 + 4, 0x002081FC);

	_regwrite(gmu->pdc_reg_virt, PDC_GPU_SEQ_MEM_0 + 4, 0x002081FC);





	/* Set TCS commands used by PDC sequence for low power modes */

	/* Set TCS commands used by PDC sequence for low power modes */

	_regwrite(gmu->pdc_reg_virt, PDC_GPU_TCS0_CMD_ENABLE_BANK, 7);

	_regwrite(gmu->pdc_reg_virt, PDC_GPU_TCS0_CMD_WAIT_FOR_CMPL_BANK, 0);

	_regwrite(gmu->pdc_reg_virt, PDC_GPU_TCS0_CONTROL, 0);

	_regwrite(gmu->pdc_reg_virt, PDC_GPU_TCS0_CMD0_MSGID, 0x10108);

	_regwrite(gmu->pdc_reg_virt, PDC_GPU_TCS0_CMD0_ADDR, 0x30010);

	_regwrite(gmu->pdc_reg_virt, PDC_GPU_TCS0_CMD0_DATA, 1);

	_regwrite(gmu->pdc_reg_virt,

			PDC_GPU_TCS0_CMD0_MSGID + PDC_CMD_OFFSET, 0x10108);

	_regwrite(gmu->pdc_reg_virt,

			PDC_GPU_TCS0_CMD0_ADDR + PDC_CMD_OFFSET, 0x30000);

	_regwrite(gmu->pdc_reg_virt,

			PDC_GPU_TCS0_CMD0_DATA + PDC_CMD_OFFSET, 0x0);

	_regwrite(gmu->pdc_reg_virt,

			PDC_GPU_TCS0_CMD0_MSGID + PDC_CMD_OFFSET * 2, 0x10108);

	_regwrite(gmu->pdc_reg_virt,

			PDC_GPU_TCS0_CMD0_ADDR + PDC_CMD_OFFSET * 2, 0x30080);

	_regwrite(gmu->pdc_reg_virt,

			PDC_GPU_TCS0_CMD0_DATA + PDC_CMD_OFFSET * 2, 0x0);

	_regwrite(gmu->pdc_reg_virt, PDC_GPU_TCS1_CMD_ENABLE_BANK, 7);

	_regwrite(gmu->pdc_reg_virt, PDC_GPU_TCS1_CMD_ENABLE_BANK, 7);

	_regwrite(gmu->pdc_reg_virt, PDC_GPU_TCS1_CMD_WAIT_FOR_CMPL_BANK, 0);

	_regwrite(gmu->pdc_reg_virt, PDC_GPU_TCS1_CMD_WAIT_FOR_CMPL_BANK, 0);

	_regwrite(gmu->pdc_reg_virt, PDC_GPU_TCS1_CONTROL, 0);

	_regwrite(gmu->pdc_reg_virt, PDC_GPU_TCS1_CONTROL, 0);

	_regwrite(gmu->pdc_reg_virt, PDC_GPU_TCS1_CMD0_MSGID, 0x10108);

	_regwrite(gmu->pdc_reg_virt, PDC_GPU_TCS1_CMD0_MSGID, 0x10108);

	_regwrite(gmu->pdc_reg_virt, PDC_GPU_TCS1_CMD0_ADDR, 0x30010);

	_regwrite(gmu->pdc_reg_virt, PDC_GPU_TCS1_CMD0_ADDR, 0x30010);

	_regwrite(gmu->pdc_reg_virt, PDC_GPU_TCS1_CMD0_DATA, 2);

	_regwrite(gmu->pdc_reg_virt, PDC_GPU_TCS1_CMD0_DATA, 1);

	_regwrite(gmu->pdc_reg_virt,

	_regwrite(gmu->pdc_reg_virt,

			PDC_GPU_TCS1_CMD0_MSGID + PDC_CMD_OFFSET, 0x10108);

			PDC_GPU_TCS1_CMD0_MSGID + PDC_CMD_OFFSET, 0x10108);

	_regwrite(gmu->pdc_reg_virt,

	_regwrite(gmu->pdc_reg_virt,

			PDC_GPU_TCS1_CMD0_ADDR + PDC_CMD_OFFSET, 0x30000);

			PDC_GPU_TCS1_CMD0_ADDR + PDC_CMD_OFFSET, 0x30000);

	_regwrite(gmu->pdc_reg_virt,

	_regwrite(gmu->pdc_reg_virt,

			PDC_GPU_TCS1_CMD0_DATA + PDC_CMD_OFFSET, 0x3);

			PDC_GPU_TCS1_CMD0_DATA + PDC_CMD_OFFSET, 0x0);

	_regwrite(gmu->pdc_reg_virt,

	_regwrite(gmu->pdc_reg_virt,

			PDC_GPU_TCS1_CMD0_MSGID + PDC_CMD_OFFSET * 2, 0x10108);

			PDC_GPU_TCS1_CMD0_MSGID + PDC_CMD_OFFSET * 2, 0x10108);

	_regwrite(gmu->pdc_reg_virt,

	_regwrite(gmu->pdc_reg_virt,

			PDC_GPU_TCS1_CMD0_ADDR + PDC_CMD_OFFSET * 2, 0x30080);

			PDC_GPU_TCS1_CMD0_ADDR + PDC_CMD_OFFSET * 2, 0x30080);

	_regwrite(gmu->pdc_reg_virt,

	_regwrite(gmu->pdc_reg_virt,

			PDC_GPU_TCS1_CMD0_DATA + PDC_CMD_OFFSET * 2, 0x3);

			PDC_GPU_TCS1_CMD0_DATA + PDC_CMD_OFFSET * 2, 0x0);

	_regwrite(gmu->pdc_reg_virt, PDC_GPU_TCS3_CMD_ENABLE_BANK, 7);

	_regwrite(gmu->pdc_reg_virt, PDC_GPU_TCS3_CMD_WAIT_FOR_CMPL_BANK, 0);

	_regwrite(gmu->pdc_reg_virt, PDC_GPU_TCS3_CONTROL, 0);

	_regwrite(gmu->pdc_reg_virt, PDC_GPU_TCS3_CMD0_MSGID, 0x10108);

	_regwrite(gmu->pdc_reg_virt, PDC_GPU_TCS3_CMD0_ADDR, 0x30010);

	_regwrite(gmu->pdc_reg_virt, PDC_GPU_TCS3_CMD0_DATA, 2);

	_regwrite(gmu->pdc_reg_virt,

			PDC_GPU_TCS3_CMD0_MSGID + PDC_CMD_OFFSET, 0x10108);

	_regwrite(gmu->pdc_reg_virt,

			PDC_GPU_TCS3_CMD0_ADDR + PDC_CMD_OFFSET, 0x30000);

	_regwrite(gmu->pdc_reg_virt,

			PDC_GPU_TCS3_CMD0_DATA + PDC_CMD_OFFSET, 0x3);

	_regwrite(gmu->pdc_reg_virt,

			PDC_GPU_TCS3_CMD0_MSGID + PDC_CMD_OFFSET * 2, 0x10108);

	_regwrite(gmu->pdc_reg_virt,

			PDC_GPU_TCS3_CMD0_ADDR + PDC_CMD_OFFSET * 2, 0x30080);

	_regwrite(gmu->pdc_reg_virt,

			PDC_GPU_TCS3_CMD0_DATA + PDC_CMD_OFFSET * 2, 0x3);





	/* Setup GPU PDC */

	/* Setup GPU PDC */

	_regwrite(gmu->pdc_reg_virt, PDC_GPU_SEQ_START_ADDR, 0);

	_regwrite(gmu->pdc_reg_virt, PDC_GPU_SEQ_START_ADDR, 0);