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Commit 868eb616 authored by Ezequiel Garcia's avatar Ezequiel Garcia Committed by Jason Cooper
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watchdog: orion: Make RSTOUT register a separate resource 



In order to support other SoC, it's required to distinguish
the 'control' timer register, from the 'rstout' register
that enables system reset on watchdog expiration.

To prevent a compatibility break, this commit adds a fallback
to a hardcoded RSTOUT address.

Reviewed-by: default avatarGuenter Roeck <linux@roeck-us.net>
Tested-by: default avatarSebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Tested-by: default avatarWilly Tarreau <w@1wt.eu>
Signed-off-by: default avatarEzequiel Garcia <ezequiel.garcia@free-electrons.com>
Acked-by: default avatarWim Van Sebroeck <wim@iguana.be>
Tested-By: default avatarJason Gunthorpe <jgunthorpe@obsidianresearch.com>
Signed-off-by: default avatarJason Cooper <jason@lakedaemon.net>
parent e97662e1

Documentation/devicetree/bindings/watchdog/marvel.txt

+4 −2
Original line number Original line Diff line number Diff line
@@ -3,7 +3,9 @@ 
Required Properties:

Required Properties:





- Compatibility : "marvell,orion-wdt"

- Compatibility : "marvell,orion-wdt"

- reg		: Address of the timer registers

- reg		: Should contain two entries: first one with the

		  timer control address, second one with the

		  rstout enable address.





Optional properties:

Optional properties:
@@ -14,7 +16,7 @@ Example: 




	wdt@20300 {

	wdt@20300 {

		compatible = "marvell,orion-wdt";

		compatible = "marvell,orion-wdt";

		reg = <0x20300 0x28>;

		reg = <0x20300 0x28>, <0x20108 0x4>;

		interrupts = <3>;

		interrupts = <3>;

		timeout-sec = <10>;

		timeout-sec = <10>;

		status = "okay";

		status = "okay";

arch/arm/mach-dove/include/mach/bridge-regs.h

+1 −0
Original line number Original line Diff line number Diff line
@@ -21,6 +21,7 @@ 
#define  CPU_CTRL_PCIE1_LINK	0x00000008

#define  CPU_CTRL_PCIE1_LINK	0x00000008





#define RSTOUTn_MASK		(BRIDGE_VIRT_BASE + 0x0108)

#define RSTOUTn_MASK		(BRIDGE_VIRT_BASE + 0x0108)

#define RSTOUTn_MASK_PHYS	(BRIDGE_PHYS_BASE + 0x0108)

#define  SOFT_RESET_OUT_EN	0x00000004

#define  SOFT_RESET_OUT_EN	0x00000004





#define SYSTEM_SOFT_RESET	(BRIDGE_VIRT_BASE + 0x010c)

#define SYSTEM_SOFT_RESET	(BRIDGE_VIRT_BASE + 0x010c)

arch/arm/mach-kirkwood/include/mach/bridge-regs.h

+1 −0
Original line number Original line Diff line number Diff line
@@ -21,6 +21,7 @@ 
#define CPU_RESET		0x00000002

#define CPU_RESET		0x00000002





#define RSTOUTn_MASK		(BRIDGE_VIRT_BASE + 0x0108)

#define RSTOUTn_MASK		(BRIDGE_VIRT_BASE + 0x0108)

#define RSTOUTn_MASK_PHYS	(BRIDGE_PHYS_BASE + 0x0108)

#define SOFT_RESET_OUT_EN	0x00000004

#define SOFT_RESET_OUT_EN	0x00000004





#define SYSTEM_SOFT_RESET	(BRIDGE_VIRT_BASE + 0x010c)

#define SYSTEM_SOFT_RESET	(BRIDGE_VIRT_BASE + 0x010c)

arch/arm/mach-mv78xx0/include/mach/bridge-regs.h

+1 −0
Original line number Original line Diff line number Diff line
@@ -15,6 +15,7 @@ 
#define L2_WRITETHROUGH		0x00020000

#define L2_WRITETHROUGH		0x00020000





#define RSTOUTn_MASK		(BRIDGE_VIRT_BASE + 0x0108)

#define RSTOUTn_MASK		(BRIDGE_VIRT_BASE + 0x0108)

#define RSTOUTn_MASK_PHYS	(BRIDGE_PHYS_BASE + 0x0108)

#define SOFT_RESET_OUT_EN	0x00000004

#define SOFT_RESET_OUT_EN	0x00000004





#define SYSTEM_SOFT_RESET	(BRIDGE_VIRT_BASE + 0x010c)

#define SYSTEM_SOFT_RESET	(BRIDGE_VIRT_BASE + 0x010c)

arch/arm/mach-orion5x/include/mach/bridge-regs.h

+1 −0
Original line number Original line Diff line number Diff line
@@ -18,6 +18,7 @@ 
#define CPU_CTRL		(ORION5X_BRIDGE_VIRT_BASE + 0x104)

#define CPU_CTRL		(ORION5X_BRIDGE_VIRT_BASE + 0x104)





#define RSTOUTn_MASK		(ORION5X_BRIDGE_VIRT_BASE + 0x108)

#define RSTOUTn_MASK		(ORION5X_BRIDGE_VIRT_BASE + 0x108)

#define RSTOUTn_MASK_PHYS	(ORION5X_BRIDGE_PHYS_BASE + 0x108)





#define CPU_SOFT_RESET		(ORION5X_BRIDGE_VIRT_BASE + 0x10c)

#define CPU_SOFT_RESET		(ORION5X_BRIDGE_VIRT_BASE + 0x10c)