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Commit 867f7804 authored by Chen-Yu Tsai's avatar Chen-Yu Tsai Committed by Greg Kroah-Hartman
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clk: sunxi-ng: sun6i: Fix enable bit offset for hdmi-ddc module clock 



commit 9ad0bb39fce319d7b92c17d306ed0a9f70a02e7d upstream.

The enable bit offset for the hdmi-ddc module clock is wrong. It is
pointing to the main hdmi module clock enable bit.

Reported-by: default avatarBob Ham <rah@settrans.net>
Fixes: c6e6c96d ("clk: sunxi-ng: Add A31/A31s clocks")
Signed-off-by: default avatarChen-Yu Tsai <wens@csie.org>
Signed-off-by: default avatarMaxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@linuxfoundation.org>
parent c445f996

drivers/clk/sunxi-ng/ccu-sun6i-a31.c

+1 −1
Original line number Diff line number Diff line
@@ -608,7 +608,7 @@ static SUNXI_CCU_M_WITH_MUX_GATE(hdmi_clk, "hdmi", lcd_ch1_parents, 
				 0x150, 0, 4, 24, 2, BIT(31),

				 CLK_SET_RATE_PARENT);



static SUNXI_CCU_GATE(hdmi_ddc_clk, "hdmi-ddc", "osc24M", 0x150, BIT(31), 0);

static SUNXI_CCU_GATE(hdmi_ddc_clk, "hdmi-ddc", "osc24M", 0x150, BIT(30), 0);



static SUNXI_CCU_GATE(ps_clk, "ps", "lcd1-ch1", 0x140, BIT(31), 0);