Merge "usb: dwc3-msm: Add sysfs node to enable SS host compliance" (867cedb3) · Commits · e / devices / android_kernel_fairphone_FP3

arch/arm/configs/sdxpoorwills_defconfig

+1 −0

Original line number	Diff line number	Diff line
		@@ -297,6 +297,7 @@ CONFIG_USB_STORAGE_KARMA=y
		CONFIG_USB_STORAGE_CYPRESS_ATACB=y
		CONFIG_USB_DWC3=y
		CONFIG_USB_DWC3_MSM=y
		CONFIG_USB_EHSET_TEST_FIXTURE=y
		CONFIG_NOP_USB_XCEIV=y
		CONFIG_USB_MSM_SSPHY_QMP=y
		CONFIG_MSM_HSUSB_PHY=y

drivers/usb/dwc3/dwc3-msm.c

+53 −0

Original line number	Diff line number	Diff line
		@@ -73,6 +73,8 @@ MODULE_PARM_DESC(cpu_to_affin, "affin usb irq to this cpu");

		/* XHCI registers */
		#define USB3_HCSPARAMS1 (0x4)
		#define USB3_HCCPARAMS2 (0x1c)
		#define HCC_CTC(p) ((p) & (1 << 3))
		#define USB3_PORTSC (0x420)

		/**
		@@ -255,6 +257,7 @@ struct dwc3_msm {
		struct notifier_block host_restart_nb;

		struct notifier_block host_nb;
		bool xhci_ss_compliance_enable;

		atomic_t in_p3;
		unsigned int lpm_to_suspend_delay;
		@@ -3286,6 +3289,35 @@ static ssize_t usb_compliance_mode_store(struct device *dev,
		static DEVICE_ATTR_RW(usb_compliance_mode);


		static ssize_t xhci_link_compliance_show(struct device *dev,
		struct device_attribute attr, char buf)
		{
		struct dwc3_msm *mdwc = dev_get_drvdata(dev);

		if (mdwc->xhci_ss_compliance_enable)
		return snprintf(buf, PAGE_SIZE, "y\n");
		else
		return snprintf(buf, PAGE_SIZE, "n\n");
		}

		static ssize_t xhci_link_compliance_store(struct device *dev,
		struct device_attribute attr, const char buf, size_t count)
		{
		struct dwc3_msm *mdwc = dev_get_drvdata(dev);
		bool value;
		int ret;

		ret = strtobool(buf, &value);
		if (!ret) {
		mdwc->xhci_ss_compliance_enable = value;
		return count;
		}

		return ret;
		}

		static DEVICE_ATTR_RW(xhci_link_compliance);

		static int dwc3_msm_probe(struct platform_device *pdev)
		{
		struct device_node node = pdev->dev.of_node, dwc3_node;
		@@ -3643,6 +3675,7 @@ static int dwc3_msm_probe(struct platform_device *pdev)
		device_create_file(&pdev->dev, &dev_attr_mode);
		device_create_file(&pdev->dev, &dev_attr_speed);
		device_create_file(&pdev->dev, &dev_attr_usb_compliance_mode);
		device_create_file(&pdev->dev, &dev_attr_xhci_link_compliance);

		host_mode = usb_get_dr_mode(&mdwc->dwc3->dev) == USB_DR_MODE_HOST;
		if (!dwc->is_drd && host_mode) {
		@@ -3681,6 +3714,7 @@ static int dwc3_msm_remove(struct platform_device *pdev)
		int ret_pm;

		device_remove_file(&pdev->dev, &dev_attr_mode);
		device_remove_file(&pdev->dev, &dev_attr_xhci_link_compliance);
		if (mdwc->usb_psy)
		power_supply_put(mdwc->usb_psy);

		@@ -3946,6 +3980,25 @@ static int dwc3_otg_start_host(struct dwc3_msm *mdwc, int on)
		return ret;
		}

		/*
		* If the Compliance Transition Capability(CTC) flag of
		* HCCPARAMS2 register is set and xhci_link_compliance sysfs
		* param has been enabled by the user for the SuperSpeed host
		* controller, then write 10 (Link in Compliance Mode State)
		* onto the Port Link State(PLS) field of the PORTSC register
		* for 3.0 host controller which is at an offset of USB3_PORTSC
		* + 0x10 from the DWC3 base address. Also, disable the runtime
		* PM of 3.0 root hub (root hub of shared_hcd of xhci device)
		*/
		if (HCC_CTC(dwc3_msm_read_reg(mdwc->base, USB3_HCCPARAMS2))
		&& mdwc->xhci_ss_compliance_enable
		&& dwc->maximum_speed == USB_SPEED_SUPER) {
		dwc3_msm_write_reg(mdwc->base, USB3_PORTSC + 0x10,
		0x10340);
		pm_runtime_disable(&hcd_to_xhci(platform_get_drvdata(
		dwc->xhci))->shared_hcd->self.root_hub->dev);
		}

		/*
		* In some cases it is observed that USB PHY is not going into
		* suspend with host mode suspend functionality. Hence disable