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Commit 85c4035e authored by Lakshmi Narayana Kalavala's avatar Lakshmi Narayana Kalavala
Browse files

msm: camera: icp: Enable camera ICP driver 



Add the support for Image control processor which routes
the requests from the user mode driver to ICP via HFI
interface. Acknowledges the response for requests
back to user mode driver.

Change-Id: I2d49463effda1d651b9cbd32ee3d24a8a67d4485
Signed-off-by: default avatarLakshmi Narayana Kalavala <lkalaval@codeaurora.org>
Signed-off-by: default avatarSagar Gore <sgore@codeaurora.org>
Signed-off-by: default avatarSuresh Vankadara <svankada@codeaurora.org>
parent 426ec66c

Documentation/devicetree/bindings/media/video/msm-cam-icp.txt

0 → 100644
+219 −0
Original line number Diff line number Diff line 
* Qualcomm Technologies, Inc. MSM Camera ICP



The MSM camera ICP devices are implemented multiple device nodes.

The root icp device node has properties defined to hint the driver

about the number of A5,IPE and BPS nodes available during the

probe sequence. Each node has multiple properties defined

for interrupts, clocks and regulators.



=======================

Required Node Structure

=======================

ICP root interface node takes care of the handling account for number

of A5, IPE and BPS devices present on the hardware.



- compatible

  Usage: required

  Value type: <string>

  Definition: Should be "qcom,cam-icp".



- compat-hw-name



  Usage: required

  Value type: <string>

  Definition: Should be "qcom,a5" or "qcom,ipe".



- num-a5

  Usage: required

  Value type: <u32>

  Definition: Number of supported A5 processors.



- num-ipe

  Usage: required

  Value type: <u32>

  Definition: Number of supported IPE HW blocks.



- num-bps

  Usage: required

  Value type: <u32>

  Definition: Number of supported BPS HW blocks.



Example:

	qcom,cam-icp {

		compatible = "qcom,cam-icp";

		compat-hw-name = "qcom,a5", "qcom,ipe0", "qcom,ipe1", "qcom,bps";

		num-a5 = <1>;

		num-ipe = <2>;

		num-bps = <1>;

		status = "ok";

	};



=======================

Required Node Structure

=======================

A5/IPE/BPS Node's provides interface for Image Control Processor driver

about the A5 register map, interrupt map, clocks, regulators

and name of firmware image.



- cell-index

  Usage: required

  Value type: <u32>

  Definition: Node instance number.



- compatible

  Usage: required

  Value type: <string>

  Definition: Should be "qcom,cam-cdm-intf".



- reg-names

  Usage: optional

  Value type: <string>

  Definition: Name of the register resources.



- reg

  Usage: optional

  Value type: <u32>

  Definition: Register values.



- reg-cam-base

  Usage: optional

  Value type: <u32>

  Definition: Register values.



- interrupt-names

  Usage: optional

  Value type: <string>

  Definition: Name of the interrupt.



- interrupts

  Usage: optional

  Value type: <u32>

  Definition: Interrupt associated with CDM HW.



- regulator-names

  Usage: required

  Value type: <string>

  Definition: Name of the regulator resources for CDM HW.



- camss-supply

  Usage: required

  Value type: <phandle>

  Definition: Regulator reference corresponding to the names listed

              in "regulator-names".



- clock-names

  Usage: required

  Value type: <string>

  Definition: List of clock names required for CDM HW.



- clocks

  Usage: required

  Value type: <phandle>

  Definition: List of clocks used for CDM HW.



- clock-rates

  Usage: required

  Value type: <u32>

  Definition: List of clocks rates.



- fw_name

  Usage: optional

  Value type: <string>

  Definition: Name of firmware image.



Examples:

a5: qcom,a5@a10000 {

	cell-index = <0>;

	compatible = "qcom,cam_a5";

	reg = <0xac00000 0x6000>,

		<0xac10000 0x8000>,

		<0xac18000 0x3000>;

	reg-names = "a5_qgic", "a5_sierra", "a5_csr";

	interrupts = <0 463 0>;

	interrupt-names = "a5";

	regulator-names = "camss-vdd";

	camss-vdd-supply = <&titan_top_gdsc>;

	clock-names = "gcc_cam_ahb_clk",

		"gcc_cam_axi_clk",

		"soc_ahb_clk",

		"cpas_ahb_clk",

		"camnoc_axi_clk",

		"icp_apb_clk",

		"icp_atb_clk",

		"icp_clk",

		"icp_clk_src",

		"icp_cti_clk",

		"icp_ts_clk";

	clocks = <&clock_gcc GCC_CAMERA_AHB_CLK>,

			<&clock_gcc GCC_CAMERA_AXI_CLK>,

			<&clock_camcc CAM_CC_SOC_AHB_CLK>,

			<&clock_camcc CAM_CC_CPAS_AHB_CLK>,

			<&clock_camcc CAM_CC_CAMNOC_AXI_CLK>,

			<&clock_camcc CAM_CC_ICP_APB_CLK>,

			<&clock_camcc CAM_CC_ICP_ATB_CLK>,

			<&clock_camcc CAM_CC_ICP_CLK>,

			<&clock_camcc CAM_CC_ICP_CLK_SRC>,

			<&clock_camcc CAM_CC_ICP_CTI_CLK>,

			<&clock_camcc CAM_CC_ICP_TS_CLK>;



	clock-rates = <0 0 0 80000000 0 0 0 0 600000000 0 0>;

	fw_name = "CAMERA_ICP.elf";

};



qcom,ipe0 {

	cell-index = <0>;

	compatible = "qcom,cam_ipe";

	regulator-names = "ipe0-vdd";

	ipe0-vdd-supply = <&ipe_0_gdsc>;

	clock-names = "ipe_0_ahb_clk",

		"ipe_0_areg_clk",

		"ipe_0_axi_clk",

		"ipe_0_clk",

		"ipe_0_clk_src";

	clocks = <&clock_camcc CAM_CC_IPE_0_AHB_CLK>,

			<&clock_camcc CAM_CC_IPE_0_AREG_CLK>,

			<&clock_camcc CAM_CC_IPE_0_AXI_CLK>,

			<&clock_camcc CAM_CC_IPE_0_CLK>,

			<&clock_camcc CAM_CC_IPE_0_CLK_SRC>;



	clock-rates = <80000000 400000000 0 0 600000000>;

};



qcom,ipe1 {

	cell-index = <1>;

	compatible = "qcom,cam_ipe";

	regulator-names = "ipe1-vdd";

	ipe1-vdd-supply = <&ipe_1_gdsc>;

	clock-names = "ipe_1_ahb_clk",

		"ipe_1_areg_clk",

		"ipe_1_axi_clk",

		"ipe_1_clk",

		"ipe_1_clk_src";

	clocks = <&clock_camcc CAM_CC_IPE_1_AHB_CLK>,

			<&clock_camcc CAM_CC_IPE_1_AREG_CLK>,

			<&clock_camcc CAM_CC_IPE_1_AXI_CLK>,

			<&clock_camcc CAM_CC_IPE_1_CLK>,

			<&clock_camcc CAM_CC_IPE_1_CLK_SRC>;



		clock-rates = <80000000 400000000 0 0 600000000>;

};



bps: qcom,bps {

	cell-index = <0>;

	compatible = "qcom,cam_bps";

	regulator-names = "bps-vdd";

	bps-vdd-supply = <&bps_gdsc>;

	clock-names = "bps_ahb_clk",

		"bps_areg_clk",

		"bps_axi_clk",

		"bps_clk",

		"bps_clk_src";

	clocks = <&clock_camcc CAM_CC_BPS_AHB_CLK>,

			<&clock_camcc CAM_CC_BPS_AREG_CLK>,

			<&clock_camcc CAM_CC_BPS_AXI_CLK>,

			<&clock_camcc CAM_CC_BPS_CLK>,

			<&clock_camcc CAM_CC_BPS_CLK_SRC>;



	clock-rates = <80000000 400000000 0 0 600000000>;

};

drivers/media/platform/msm/camera/Makefile

+1 −0
Original line number Diff line number Diff line
@@ -7,3 +7,4 @@ obj-$(CONFIG_SPECTRA_CAMERA) += cam_cpas/ 
obj-$(CONFIG_SPECTRA_CAMERA) += cam_cdm/

obj-$(CONFIG_SPECTRA_CAMERA) += cam_isp/

obj-$(CONFIG_SPECTRA_CAMERA) += cam_sensor_module/

obj-$(CONFIG_SPECTRA_CAMERA) += icp/

drivers/media/platform/msm/camera/cam_core/Makefile

+2 −1
Original line number Diff line number Diff line 
ccflags-y += -Idrivers/media/platform/msm/camera/cam_req_mgr

ccflags-y += -Idrivers/media/platform/msm/camera/cam_sync



obj-$(CONFIG_SPECTRA_CAMERA) += cam_context.o cam_node.o cam_subdev.o
 
obj-$(CONFIG_SPECTRA_CAMERA) += cam_context.o cam_context_utils.o cam_node.o cam_subdev.o

drivers/media/platform/msm/camera/cam_core/cam_context.c

+0 −1
Original line number Diff line number Diff line
@@ -358,4 +358,3 @@ int cam_context_deinit(struct cam_context *ctx) 


	return 0;

}

drivers/media/platform/msm/camera/cam_core/cam_context.h

+24 −4
Original line number Diff line number Diff line
@@ -22,6 +22,8 @@ struct cam_context; 


/* max request number */

#define CAM_CTX_REQ_MAX              20

#define CAM_CTX_CFG_MAX              20

#define CAM_CTX_RES_MAX              20



/**

 * enum cam_ctx_state -  context top level states
@@ -43,6 +45,14 @@ enum cam_context_state { 
 * @status:                Request status

 * @request_id:            Request id

 * @req_priv:              Derived request object

 * @hw_update_entries:     Hardware update entries

 * @num_hw_update_entries: Number of hardware update entries

 * @in_map_entries:        Entries for in fences

 * @num_in_map_entries:    Number of in map entries

 * @out_map_entries:       Entries for out fences

 * @num_out_map_entries:   Number of out map entries

 * @num_in_acked:          Number of in fence acked

 * @num_out_acked:         Number of out fence acked

 *

 */

struct cam_ctx_request {
@@ -50,6 +60,14 @@ struct cam_ctx_request { 
	uint32_t                      status;

	uint64_t                      request_id;

	void                          *req_priv;

	struct cam_hw_update_entry    hw_update_entries[CAM_CTX_CFG_MAX];

	uint32_t                      num_hw_update_entries;

	struct cam_hw_fence_map_entry in_map_entries[CAM_CTX_CFG_MAX];

	uint32_t                      num_in_map_entries;

	struct cam_hw_fence_map_entry out_map_entries[CAM_CTX_CFG_MAX];

	uint32_t                      num_out_map_entries;

	uint32_t                      num_in_acked;

	uint32_t                      num_out_acked;

};



/**
@@ -132,6 +150,7 @@ struct cam_ctx_ops { 
 * @state:                 Current state for top level state machine

 * @state_machine:         Top level state machine

 * @ctx_priv:              Private context pointer

 * @ctxt_to_hw_map:        Context to hardware mapping pointer

 *

 */

struct cam_context {
@@ -159,6 +178,7 @@ struct cam_context { 
	struct cam_ctx_ops          *state_machine;



	void                        *ctx_priv;

	void                        *ctxt_to_hw_map;

};



/**