Loading drivers/gpu/drm/msm/sde/sde_encoder.c +27 −5 Original line number Diff line number Diff line Loading @@ -2348,6 +2348,7 @@ static void sde_encoder_virt_disable(struct drm_encoder *drm_enc) struct msm_drm_private *priv; struct sde_kms *sde_kms; struct drm_connector *drm_conn = NULL; enum sde_intf_mode intf_mode; int i = 0; if (!drm_enc) { Loading @@ -2366,6 +2367,7 @@ static void sde_encoder_virt_disable(struct drm_encoder *drm_enc) priv = drm_enc->dev->dev_private; sde_kms = to_sde_kms(priv->kms); intf_mode = sde_encoder_get_intf_mode(drm_enc); SDE_EVT32(DRMID(drm_enc)); Loading @@ -2376,14 +2378,34 @@ static void sde_encoder_virt_disable(struct drm_encoder *drm_enc) /* wait for idle */ sde_encoder_wait_for_event(drm_enc, MSM_ENC_TX_COMPLETE); sde_encoder_resource_control(drm_enc, SDE_ENC_RC_EVENT_PRE_STOP); /* * For primary command mode encoders, execute the resource control * pre-stop operations before the physical encoders are disabled, to * allow the rsc to transition its states properly. * * For other encoder types, rsc should not be enabled until after * they have been fully disabled, so delay the pre-stop operations * until after the physical disable calls have returned. */ if (sde_enc->disp_info.is_primary && intf_mode == INTF_MODE_CMD) { sde_encoder_resource_control(drm_enc, SDE_ENC_RC_EVENT_PRE_STOP); for (i = 0; i < sde_enc->num_phys_encs; i++) { struct sde_encoder_phys *phys = sde_enc->phys_encs[i]; if (phys && phys->ops.disable) phys->ops.disable(phys); } } else { for (i = 0; i < sde_enc->num_phys_encs; i++) { struct sde_encoder_phys *phys = sde_enc->phys_encs[i]; if (phys && phys->ops.disable) phys->ops.disable(phys); } sde_encoder_resource_control(drm_enc, SDE_ENC_RC_EVENT_PRE_STOP); } /* * disable dsc after the transfer is complete (for command mode) Loading drivers/gpu/drm/msm/sde/sde_encoder_phys_vid.c +18 −3 Original line number Diff line number Diff line Loading @@ -882,6 +882,9 @@ static void sde_encoder_phys_vid_disable(struct sde_encoder_phys *phys_enc) sde_encoder_phys_inc_pending(phys_enc); spin_unlock_irqrestore(phys_enc->enc_spinlock, lock_flags); if (!sde_encoder_phys_vid_is_master(phys_enc)) goto exit; /* * Wait for a vsync so we know the ENABLE=0 latched before * the (connector) source of the vsync's gets disabled, Loading @@ -890,7 +893,16 @@ static void sde_encoder_phys_vid_disable(struct sde_encoder_phys *phys_enc) * the settings changes for the new modeset (like new * scanout buffer) don't latch properly.. */ if (sde_encoder_phys_vid_is_master(phys_enc)) { ret = sde_encoder_phys_vid_control_vblank_irq(phys_enc, true); if (ret) { SDE_ERROR_VIDENC(vid_enc, "failed to enable vblank irq: %d\n", ret); SDE_EVT32(DRMID(phys_enc->parent), vid_enc->hw_intf->idx - INTF_0, ret, SDE_EVTLOG_FUNC_CASE1, SDE_EVTLOG_ERROR); } else { ret = _sde_encoder_phys_vid_wait_for_vblank(phys_enc, false); if (ret) { atomic_set(&phys_enc->pending_kickoff_cnt, 0); Loading @@ -898,10 +910,13 @@ static void sde_encoder_phys_vid_disable(struct sde_encoder_phys *phys_enc) "failure waiting for disable: %d\n", ret); SDE_EVT32(DRMID(phys_enc->parent), vid_enc->hw_intf->idx - INTF_0, ret); vid_enc->hw_intf->idx - INTF_0, ret, SDE_EVTLOG_FUNC_CASE2, SDE_EVTLOG_ERROR); } sde_encoder_phys_vid_control_vblank_irq(phys_enc, false); } exit: phys_enc->enable_state = SDE_ENC_DISABLED; } Loading Loading
drivers/gpu/drm/msm/sde/sde_encoder.c +27 −5 Original line number Diff line number Diff line Loading @@ -2348,6 +2348,7 @@ static void sde_encoder_virt_disable(struct drm_encoder *drm_enc) struct msm_drm_private *priv; struct sde_kms *sde_kms; struct drm_connector *drm_conn = NULL; enum sde_intf_mode intf_mode; int i = 0; if (!drm_enc) { Loading @@ -2366,6 +2367,7 @@ static void sde_encoder_virt_disable(struct drm_encoder *drm_enc) priv = drm_enc->dev->dev_private; sde_kms = to_sde_kms(priv->kms); intf_mode = sde_encoder_get_intf_mode(drm_enc); SDE_EVT32(DRMID(drm_enc)); Loading @@ -2376,14 +2378,34 @@ static void sde_encoder_virt_disable(struct drm_encoder *drm_enc) /* wait for idle */ sde_encoder_wait_for_event(drm_enc, MSM_ENC_TX_COMPLETE); sde_encoder_resource_control(drm_enc, SDE_ENC_RC_EVENT_PRE_STOP); /* * For primary command mode encoders, execute the resource control * pre-stop operations before the physical encoders are disabled, to * allow the rsc to transition its states properly. * * For other encoder types, rsc should not be enabled until after * they have been fully disabled, so delay the pre-stop operations * until after the physical disable calls have returned. */ if (sde_enc->disp_info.is_primary && intf_mode == INTF_MODE_CMD) { sde_encoder_resource_control(drm_enc, SDE_ENC_RC_EVENT_PRE_STOP); for (i = 0; i < sde_enc->num_phys_encs; i++) { struct sde_encoder_phys *phys = sde_enc->phys_encs[i]; if (phys && phys->ops.disable) phys->ops.disable(phys); } } else { for (i = 0; i < sde_enc->num_phys_encs; i++) { struct sde_encoder_phys *phys = sde_enc->phys_encs[i]; if (phys && phys->ops.disable) phys->ops.disable(phys); } sde_encoder_resource_control(drm_enc, SDE_ENC_RC_EVENT_PRE_STOP); } /* * disable dsc after the transfer is complete (for command mode) Loading
drivers/gpu/drm/msm/sde/sde_encoder_phys_vid.c +18 −3 Original line number Diff line number Diff line Loading @@ -882,6 +882,9 @@ static void sde_encoder_phys_vid_disable(struct sde_encoder_phys *phys_enc) sde_encoder_phys_inc_pending(phys_enc); spin_unlock_irqrestore(phys_enc->enc_spinlock, lock_flags); if (!sde_encoder_phys_vid_is_master(phys_enc)) goto exit; /* * Wait for a vsync so we know the ENABLE=0 latched before * the (connector) source of the vsync's gets disabled, Loading @@ -890,7 +893,16 @@ static void sde_encoder_phys_vid_disable(struct sde_encoder_phys *phys_enc) * the settings changes for the new modeset (like new * scanout buffer) don't latch properly.. */ if (sde_encoder_phys_vid_is_master(phys_enc)) { ret = sde_encoder_phys_vid_control_vblank_irq(phys_enc, true); if (ret) { SDE_ERROR_VIDENC(vid_enc, "failed to enable vblank irq: %d\n", ret); SDE_EVT32(DRMID(phys_enc->parent), vid_enc->hw_intf->idx - INTF_0, ret, SDE_EVTLOG_FUNC_CASE1, SDE_EVTLOG_ERROR); } else { ret = _sde_encoder_phys_vid_wait_for_vblank(phys_enc, false); if (ret) { atomic_set(&phys_enc->pending_kickoff_cnt, 0); Loading @@ -898,10 +910,13 @@ static void sde_encoder_phys_vid_disable(struct sde_encoder_phys *phys_enc) "failure waiting for disable: %d\n", ret); SDE_EVT32(DRMID(phys_enc->parent), vid_enc->hw_intf->idx - INTF_0, ret); vid_enc->hw_intf->idx - INTF_0, ret, SDE_EVTLOG_FUNC_CASE2, SDE_EVTLOG_ERROR); } sde_encoder_phys_vid_control_vblank_irq(phys_enc, false); } exit: phys_enc->enable_state = SDE_ENC_DISABLED; } Loading