Loading drivers/clk/qcom/clk-alpha-pll.c +472 −17 Original line number Original line Diff line number Diff line Loading @@ -22,6 +22,8 @@ #include "clk-alpha-pll.h" #include "clk-alpha-pll.h" #define PLL_MODE 0x00 #define PLL_MODE 0x00 #define PLL_STANDBY 0x0 #define PLL_RUN 0x1 # define PLL_OUTCTRL BIT(0) # define PLL_OUTCTRL BIT(0) # define PLL_BYPASSNL BIT(1) # define PLL_BYPASSNL BIT(1) # define PLL_RESET_N BIT(2) # define PLL_RESET_N BIT(2) Loading Loading @@ -51,25 +53,40 @@ #define PLL_TEST_CTL 0x1c #define PLL_TEST_CTL 0x1c #define PLL_TEST_CTL_U 0x20 #define PLL_TEST_CTL_U 0x20 #define PLL_STATUS 0x24 #define PLL_STATUS 0x24 #define PLL_UPDATE BIT(22) #define PLL_ACK_LATCH BIT(29) #define PLL_CALIBRATION_MASK (0x7<<3) #define PLL_CALIBRATION_CONTROL 2 #define PLL_HW_UPDATE_LOGIC_BYPASS BIT(23) #define ALPHA_16_BIT_PLL_RATE_MARGIN 500 /* /* * Even though 40 bits are present, use only 32 for ease of calculation. * Even though 40 bits are present, use only 32 for ease of calculation. */ */ #define ALPHA_REG_BITWIDTH 40 #define ALPHA_REG_BITWIDTH 40 #define ALPHA_BITWIDTH 32 #define ALPHA_BITWIDTH 32 #define FABIA_BITWIDTH 16 #define SUPPORTS_16BIT_ALPHA 16 #define FABIA_USER_CTL_LO 0xc #define FABIA_USER_CTL_LO 0xc #define FABIA_USER_CTL_HI 0x10 #define FABIA_USER_CTL_HI 0x10 #define FABIA_FRAC_VAL 0x38 #define FABIA_FRAC_VAL 0x38 #define FABIA_OPMODE 0x2c #define FABIA_OPMODE 0x2c #define FABIA_PLL_STANDBY 0x0 #define FABIA_PLL_RUN 0x1 #define FABIA_PLL_OUT_MASK 0x7 #define FABIA_PLL_OUT_MASK 0x7 #define FABIA_PLL_RATE_MARGIN 500 #define FABIA_PLL_ACK_LATCH BIT(29) #define FABIA_PLL_ACK_LATCH BIT(29) #define FABIA_PLL_UPDATE BIT(22) #define FABIA_PLL_UPDATE BIT(22) #define FABIA_PLL_HW_UPDATE_LOGIC_BYPASS BIT(23) #define TRION_PLL_CAL_VAL 0x44 #define TRION_PLL_CAL_L_VAL 0x8 #define TRION_PLL_USER_CTL 0xc #define TRION_PLL_USER_CTL_U 0x10 #define TRION_PLL_USER_CTL_U1 0x14 #define TRION_PLL_CONFIG_CTL_U 0x1c #define TRION_PLL_CONFIG_CTL_U1 0x20 #define TRION_PLL_OPMODE 0x38 #define TRION_PLL_ALPHA_VAL 0x40 #define TRION_PLL_OUT_MASK 0x7 #define TRION_PLL_ENABLE_STATE_READ BIT(4) #define to_clk_alpha_pll(_hw) container_of(to_clk_regmap(_hw), \ #define to_clk_alpha_pll(_hw) container_of(to_clk_regmap(_hw), \ struct clk_alpha_pll, clkr) struct clk_alpha_pll, clkr) Loading Loading @@ -121,6 +138,10 @@ static int wait_for_pll_offline(struct clk_alpha_pll *pll, u32 mask) return wait_for_pll(pll, mask, 0, "offline"); return wait_for_pll(pll, mask, 0, "offline"); } } static int wait_for_pll_latch_ack(struct clk_alpha_pll *pll, u32 mask) { return wait_for_pll(pll, mask, 0, "latch_ack"); } /* alpha pll with hwfsm support */ /* alpha pll with hwfsm support */ Loading Loading @@ -294,8 +315,8 @@ static unsigned long alpha_pll_calc_rate(const struct clk_alpha_pll *pll, { { int alpha_bw = ALPHA_BITWIDTH; int alpha_bw = ALPHA_BITWIDTH; if (pll->type == FABIA_PLL) if (pll->type == FABIA_PLL || pll->type == TRION_PLL) alpha_bw = FABIA_BITWIDTH; alpha_bw = SUPPORTS_16BIT_ALPHA; return (prate * l) + ((prate * a) >> alpha_bw); return (prate * l) + ((prate * a) >> alpha_bw); } } Loading Loading @@ -326,9 +347,9 @@ alpha_pll_round_rate(const struct clk_alpha_pll *pll, unsigned long rate, return rate; return rate; } } /* Fabia PLLs only have 16 bits to program the fractional divider */ /* Some PLLs only have 16 bits to program the fractional divider */ if (pll->type == FABIA_PLL) if (pll->type == FABIA_PLL || pll->type == TRION_PLL) alpha_bw = FABIA_BITWIDTH; alpha_bw = SUPPORTS_16BIT_ALPHA; /* Upper ALPHA_BITWIDTH bits of Alpha */ /* Upper ALPHA_BITWIDTH bits of Alpha */ quotient = remainder << alpha_bw; quotient = remainder << alpha_bw; Loading Loading @@ -415,7 +436,8 @@ static long clk_alpha_pll_round_rate(struct clk_hw *hw, unsigned long rate, unsigned long min_freq, max_freq; unsigned long min_freq, max_freq; rate = alpha_pll_round_rate(pll, rate, *prate, &l, &a); rate = alpha_pll_round_rate(pll, rate, *prate, &l, &a); if (pll->type == FABIA_PLL || alpha_pll_find_vco(pll, rate)) if (pll->type == FABIA_PLL || pll->type == TRION_PLL || alpha_pll_find_vco(pll, rate)) return rate; return rate; min_freq = pll->vco_table[0].min_freq; min_freq = pll->vco_table[0].min_freq; Loading Loading @@ -523,8 +545,8 @@ void clk_fabia_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, clk_fabia_pll_latch_input(pll, regmap); clk_fabia_pll_latch_input(pll, regmap); regmap_update_bits(regmap, pll->offset + PLL_MODE, regmap_update_bits(regmap, pll->offset + PLL_MODE, FABIA_PLL_HW_UPDATE_LOGIC_BYPASS, PLL_HW_UPDATE_LOGIC_BYPASS, FABIA_PLL_HW_UPDATE_LOGIC_BYPASS); PLL_HW_UPDATE_LOGIC_BYPASS); regmap_update_bits(regmap, pll->offset + PLL_MODE, regmap_update_bits(regmap, pll->offset + PLL_MODE, PLL_RESET_N, PLL_RESET_N); PLL_RESET_N, PLL_RESET_N); Loading Loading @@ -560,7 +582,7 @@ static int clk_fabia_pll_enable(struct clk_hw *hw) return ret; return ret; /* Set operation mode to STANDBY */ /* Set operation mode to STANDBY */ regmap_write(pll->clkr.regmap, off + FABIA_OPMODE, FABIA_PLL_STANDBY); regmap_write(pll->clkr.regmap, off + FABIA_OPMODE, PLL_STANDBY); /* PLL should be in STANDBY mode before continuing */ /* PLL should be in STANDBY mode before continuing */ mb(); mb(); Loading @@ -572,7 +594,7 @@ static int clk_fabia_pll_enable(struct clk_hw *hw) return ret; return ret; /* Set operation mode to RUN */ /* Set operation mode to RUN */ regmap_write(pll->clkr.regmap, off + FABIA_OPMODE, FABIA_PLL_RUN); regmap_write(pll->clkr.regmap, off + FABIA_OPMODE, PLL_RUN); ret = wait_for_pll_enable(pll, PLL_LOCK_DET); ret = wait_for_pll_enable(pll, PLL_LOCK_DET); if (ret) if (ret) Loading Loading @@ -624,7 +646,7 @@ static void clk_fabia_pll_disable(struct clk_hw *hw) return; return; /* Place the PLL mode in STANDBY */ /* Place the PLL mode in STANDBY */ regmap_write(pll->clkr.regmap, off + FABIA_OPMODE, FABIA_PLL_STANDBY); regmap_write(pll->clkr.regmap, off + FABIA_OPMODE, PLL_STANDBY); } } static unsigned long static unsigned long Loading Loading @@ -659,7 +681,7 @@ static int clk_fabia_pll_set_rate(struct clk_hw *hw, unsigned long rate, * Due to limited number of bits for fractional rate programming, the * Due to limited number of bits for fractional rate programming, the * rounded up rate could be marginally higher than the requested rate. * rounded up rate could be marginally higher than the requested rate. */ */ if (rrate > (rate + FABIA_PLL_RATE_MARGIN) || rrate < rate) { if (rrate > (rate + ALPHA_16_BIT_PLL_RATE_MARGIN) || rrate < rate) { pr_err("Call set rate on the PLL with rounded rates!\n"); pr_err("Call set rate on the PLL with rounded rates!\n"); return -EINVAL; return -EINVAL; } } Loading Loading @@ -879,3 +901,436 @@ const struct clk_ops clk_generic_pll_postdiv_ops = { .set_rate = clk_generic_pll_postdiv_set_rate, .set_rate = clk_generic_pll_postdiv_set_rate, }; }; EXPORT_SYMBOL_GPL(clk_generic_pll_postdiv_ops); EXPORT_SYMBOL_GPL(clk_generic_pll_postdiv_ops); static int trion_pll_is_enabled(struct clk_alpha_pll *pll, struct regmap *regmap) { u32 mode_val, opmode_val, off = pll->offset; int ret; ret = regmap_read(regmap, off + PLL_MODE, &mode_val); ret |= regmap_read(regmap, off + TRION_PLL_OPMODE, &opmode_val); if (ret) return 0; return ((opmode_val & PLL_RUN) && (mode_val & PLL_OUTCTRL)); } int clk_trion_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, const struct pll_config *config) { int ret = 0; if (trion_pll_is_enabled(pll, regmap)) { pr_debug("PLL is already enabled. Skipping configuration.\n"); /* * Set the PLL_HW_UPDATE_LOGIC_BYPASS bit to latch the input * before continuing. */ regmap_update_bits(regmap, pll->offset + PLL_MODE, PLL_HW_UPDATE_LOGIC_BYPASS, PLL_HW_UPDATE_LOGIC_BYPASS); pll->inited = true; return ret; } /* * Disable the PLL if it's already been initialized. Not doing so might * lead to the PLL running with the old frequency configuration. */ if (pll->inited) { ret = regmap_update_bits(regmap, pll->offset + PLL_MODE, PLL_RESET_N, 0); if (ret) return ret; } if (config->l) regmap_write(regmap, pll->offset + PLL_L_VAL, config->l); regmap_write(regmap, pll->offset + TRION_PLL_CAL_L_VAL, TRION_PLL_CAL_VAL); if (config->frac) regmap_write(regmap, pll->offset + TRION_PLL_ALPHA_VAL, config->frac); if (config->config_ctl_val) regmap_write(regmap, pll->offset + PLL_CONFIG_CTL, config->config_ctl_val); if (config->config_ctl_hi_val) regmap_write(regmap, pll->offset + TRION_PLL_CONFIG_CTL_U, config->config_ctl_hi_val); if (config->config_ctl_hi1_val) regmap_write(regmap, pll->offset + TRION_PLL_CONFIG_CTL_U1, config->config_ctl_hi1_val); if (config->post_div_mask) regmap_update_bits(regmap, pll->offset + TRION_PLL_USER_CTL, config->post_div_mask, config->post_div_val); /* Disable state read */ regmap_update_bits(regmap, pll->offset + TRION_PLL_USER_CTL_U, TRION_PLL_ENABLE_STATE_READ, 0); regmap_update_bits(regmap, pll->offset + PLL_MODE, PLL_HW_UPDATE_LOGIC_BYPASS, PLL_HW_UPDATE_LOGIC_BYPASS); /* Set calibration control to Automatic */ regmap_update_bits(regmap, pll->offset + TRION_PLL_USER_CTL_U, PLL_CALIBRATION_MASK, PLL_CALIBRATION_CONTROL); /* Disable PLL output */ ret = regmap_update_bits(regmap, pll->offset + PLL_MODE, PLL_OUTCTRL, 0); if (ret) return ret; /* Set operation mode to OFF */ regmap_write(regmap, pll->offset + TRION_PLL_OPMODE, PLL_STANDBY); /* PLL should be in OFF mode before continuing */ wmb(); /* Place the PLL in STANDBY mode */ ret = regmap_update_bits(regmap, pll->offset + PLL_MODE, PLL_RESET_N, PLL_RESET_N); if (ret) return ret; pll->inited = true; return ret; } static int clk_alpha_pll_latch_l_val(struct clk_alpha_pll *pll) { int ret; /* Latch the input to the PLL */ ret = regmap_update_bits(pll->clkr.regmap, pll->offset + PLL_MODE, PLL_UPDATE, PLL_UPDATE); if (ret) return ret; /* Wait for 2 reference cycle before checking ACK bit */ udelay(1); ret = wait_for_pll_latch_ack(pll, PLL_ACK_LATCH); if (ret) return ret; /* Return latch input to 0 */ ret = regmap_update_bits(pll->clkr.regmap, pll->offset + PLL_MODE, PLL_UPDATE, (u32)~PLL_UPDATE); if (ret) return ret; return 0; } static int clk_trion_pll_enable(struct clk_hw *hw) { int ret = 0; struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); u32 val, off = pll->offset; ret = regmap_read(pll->clkr.regmap, off + PLL_MODE, &val); if (ret) return ret; /* If in FSM mode, just vote for it */ if (val & PLL_VOTE_FSM_ENA) { ret = clk_enable_regmap(hw); if (ret) return ret; return wait_for_pll_enable(pll, PLL_ACTIVE_FLAG); } if (unlikely(!pll->inited)) { ret = clk_trion_pll_configure(pll, pll->clkr.regmap, pll->config); if (ret) { pr_err("Failed to configure %s\n", clk_hw_get_name(hw)); return ret; } } /* Skip If PLL is already running */ if (trion_pll_is_enabled(pll, pll->clkr.regmap)) return ret; /* Set operation mode to RUN */ regmap_write(pll->clkr.regmap, off + TRION_PLL_OPMODE, PLL_RUN); ret = wait_for_pll_enable(pll, PLL_LOCK_DET); if (ret) return ret; /* Enable PLL main output */ ret = regmap_update_bits(pll->clkr.regmap, off + TRION_PLL_USER_CTL, TRION_PLL_OUT_MASK, TRION_PLL_OUT_MASK); if (ret) return ret; /* Enable Global PLL outputs */ ret = regmap_update_bits(pll->clkr.regmap, off + PLL_MODE, PLL_OUTCTRL, PLL_OUTCTRL); if (ret) return ret; /* Ensure that the write above goes through before returning. */ mb(); return ret; } static void clk_trion_pll_disable(struct clk_hw *hw) { int ret; struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); u32 val, off = pll->offset; ret = regmap_read(pll->clkr.regmap, off + PLL_MODE, &val); if (ret) return; /* If in FSM mode, just unvote it */ if (val & PLL_VOTE_FSM_ENA) { clk_disable_regmap(hw); return; } /* Disable Global PLL outputs */ ret = regmap_update_bits(pll->clkr.regmap, off + PLL_MODE, PLL_OUTCTRL, 0); if (ret) return; /* Disable the main PLL output */ ret = regmap_update_bits(pll->clkr.regmap, off + TRION_PLL_USER_CTL, TRION_PLL_OUT_MASK, 0); if (ret) return; /* Place the PLL into STANDBY mode */ regmap_write(pll->clkr.regmap, off + TRION_PLL_OPMODE, PLL_STANDBY); regmap_update_bits(pll->clkr.regmap, off + PLL_MODE, PLL_RESET_N, PLL_RESET_N); } static unsigned long clk_trion_pll_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) { u32 l, frac = 0; u64 prate = parent_rate; struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); u32 off = pll->offset; regmap_read(pll->clkr.regmap, off + PLL_L_VAL, &l); regmap_read(pll->clkr.regmap, off + TRION_PLL_ALPHA_VAL, &frac); return alpha_pll_calc_rate(pll, prate, l, frac); } static int clk_trion_pll_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long prate) { struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); unsigned long rrate; bool is_enabled; int ret; u32 l, val, off = pll->offset; u64 a; rrate = alpha_pll_round_rate(pll, rate, prate, &l, &a); /* * Due to limited number of bits for fractional rate programming, the * rounded up rate could be marginally higher than the requested rate. */ if (rrate > (rate + ALPHA_16_BIT_PLL_RATE_MARGIN) || rrate < rate) { pr_err("Trion_pll: Call clk_set_rate with rounded rates!\n"); return -EINVAL; } is_enabled = clk_hw_is_enabled(hw); if (is_enabled) hw->init->ops->disable(hw); regmap_write(pll->clkr.regmap, off + PLL_L_VAL, l); regmap_write(pll->clkr.regmap, off + TRION_PLL_ALPHA_VAL, a); ret = regmap_read(pll->clkr.regmap, off + PLL_MODE, &val); if (ret) return ret; /* * If PLL is in Standby or RUN mode then only latch the L value * Else PLL is in OFF mode and just configure L register - as per * HPG no need to latch input. */ if (val & PLL_RESET_N) clk_alpha_pll_latch_l_val(pll); if (is_enabled) hw->init->ops->enable(hw); /* Wait for PLL output to stabilize */ udelay(100); return ret; } static int clk_trion_pll_is_enabled(struct clk_hw *hw) { struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); return trion_pll_is_enabled(pll, pll->clkr.regmap); } static void clk_trion_pll_list_registers(struct seq_file *f, struct clk_hw *hw) { struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); int size, i, val; static struct clk_register_data data[] = { {"PLL_MODE", 0x0}, {"PLL_L_VAL", 0x4}, {"PLL_USER_CTL", 0xc}, {"PLL_USER_CTL_U", 0x10}, {"PLL_USER_CTL_U1", 0x14}, {"PLL_CONFIG_CTL", 0x18}, {"PLL_CONFIG_CTL_U", 0x1c}, {"PLL_CONFIG_CTL_U1", 0x20}, {"PLL_OPMODE", 0x38}, }; static struct clk_register_data data1[] = { {"APSS_PLL_VOTE", 0x0}, }; size = ARRAY_SIZE(data); for (i = 0; i < size; i++) { regmap_read(pll->clkr.regmap, pll->offset + data[i].offset, &val); seq_printf(f, "%20s: 0x%.8x\n", data[i].name, val); } regmap_read(pll->clkr.regmap, pll->offset + data[0].offset, &val); if (val & PLL_VOTE_FSM_ENA) { regmap_read(pll->clkr.regmap, pll->clkr.enable_reg + data1[0].offset, &val); seq_printf(f, "%20s: 0x%.8x\n", data1[0].name, val); } } const struct clk_ops clk_trion_pll_ops = { .enable = clk_trion_pll_enable, .disable = clk_trion_pll_disable, .recalc_rate = clk_trion_pll_recalc_rate, .round_rate = clk_alpha_pll_round_rate, .set_rate = clk_trion_pll_set_rate, .is_enabled = clk_trion_pll_is_enabled, .list_registers = clk_trion_pll_list_registers, }; EXPORT_SYMBOL(clk_trion_pll_ops); const struct clk_ops clk_trion_fixed_pll_ops = { .enable = clk_trion_pll_enable, .disable = clk_trion_pll_disable, .recalc_rate = clk_trion_pll_recalc_rate, .round_rate = clk_alpha_pll_round_rate, .is_enabled = clk_trion_pll_is_enabled, .list_registers = clk_trion_pll_list_registers, }; EXPORT_SYMBOL(clk_trion_fixed_pll_ops); static unsigned long clk_trion_pll_postdiv_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) { struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw); u32 i, cal_div = 1, val; if (!pll->post_div_table) { pr_err("Missing the post_div_table for the PLL\n"); return -EINVAL; } regmap_read(pll->clkr.regmap, pll->offset + TRION_PLL_USER_CTL, &val); val >>= pll->post_div_shift; val &= PLL_POST_DIV_MASK; for (i = 0; i < pll->num_post_div; i++) { if (pll->post_div_table[i].val == val) { cal_div = pll->post_div_table[i].div; break; } } return (parent_rate / cal_div); } static long clk_trion_pll_postdiv_round_rate(struct clk_hw *hw, unsigned long rate, unsigned long *prate) { struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw); if (!pll->post_div_table) return -EINVAL; return divider_round_rate(hw, rate, prate, pll->post_div_table, pll->width, CLK_DIVIDER_ROUND_CLOSEST); } static int clk_trion_pll_postdiv_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate) { struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw); int i, val = 0, cal_div, ret; /* * If the PLL is in FSM mode, then treat the set_rate callback * as a no-operation. */ ret = regmap_read(pll->clkr.regmap, pll->offset + PLL_MODE, &val); if (ret) return ret; if (val & PLL_VOTE_FSM_ENA) return 0; if (!pll->post_div_table) { pr_err("Missing the post_div_table for the PLL\n"); return -EINVAL; } cal_div = DIV_ROUND_UP_ULL((u64)parent_rate, rate); for (i = 0; i < pll->num_post_div; i++) { if (pll->post_div_table[i].div == cal_div) { val = pll->post_div_table[i].val; break; } } return regmap_update_bits(pll->clkr.regmap, pll->offset + TRION_PLL_USER_CTL, PLL_POST_DIV_MASK << pll->post_div_shift, val << pll->post_div_shift); } const struct clk_ops clk_trion_pll_postdiv_ops = { .recalc_rate = clk_trion_pll_postdiv_recalc_rate, .round_rate = clk_trion_pll_postdiv_round_rate, .set_rate = clk_trion_pll_postdiv_set_rate, }; EXPORT_SYMBOL(clk_trion_pll_postdiv_ops); drivers/clk/qcom/clk-alpha-pll.h +8 −2 Original line number Original line Diff line number Diff line /* /* * Copyright (c) 2015-2016, The Linux Foundation. All rights reserved. * Copyright (c) 2015-2017, The Linux Foundation. All rights reserved. * * * This software is licensed under the terms of the GNU General Public * This software is licensed under the terms of the GNU General Public * License version 2, as published by the Free Software Foundation, and * License version 2, as published by the Free Software Foundation, and Loading Loading @@ -27,6 +27,7 @@ struct pll_vco { enum pll_type { enum pll_type { ALPHA_PLL, ALPHA_PLL, FABIA_PLL, FABIA_PLL, TRION_PLL, }; }; /** /** Loading @@ -35,7 +36,7 @@ enum pll_type { * @inited: flag that's set when the PLL is initialized * @inited: flag that's set when the PLL is initialized * @vco_table: array of VCO settings * @vco_table: array of VCO settings * @clkr: regmap clock handle * @clkr: regmap clock handle * @is_fabia: Set if the PLL type is FABIA * @pll_type: Specify the type of PLL */ */ struct clk_alpha_pll { struct clk_alpha_pll { u32 offset; u32 offset; Loading Loading @@ -79,10 +80,15 @@ extern const struct clk_ops clk_alpha_pll_postdiv_ops; extern const struct clk_ops clk_fabia_pll_ops; extern const struct clk_ops clk_fabia_pll_ops; extern const struct clk_ops clk_fabia_fixed_pll_ops; extern const struct clk_ops clk_fabia_fixed_pll_ops; extern const struct clk_ops clk_generic_pll_postdiv_ops; extern const struct clk_ops clk_generic_pll_postdiv_ops; extern const struct clk_ops clk_trion_pll_ops; extern const struct clk_ops clk_trion_fixed_pll_ops; extern const struct clk_ops clk_trion_pll_postdiv_ops; void clk_alpha_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, void clk_alpha_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, const struct pll_config *config); const struct pll_config *config); void clk_fabia_pll_configure(struct clk_alpha_pll *pll, void clk_fabia_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, const struct pll_config *config); struct regmap *regmap, const struct pll_config *config); int clk_trion_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, const struct pll_config *config); #endif #endif drivers/clk/qcom/clk-pll.h +3 −1 Original line number Original line Diff line number Diff line /* /* * Copyright (c) 2013, 2016, The Linux Foundation. All rights reserved. * Copyright (c) 2013, 2016-2017, The Linux Foundation. All rights reserved. * * * This software is licensed under the terms of the GNU General Public * This software is licensed under the terms of the GNU General Public * License version 2, as published by the Free Software Foundation, and * License version 2, as published by the Free Software Foundation, and Loading Loading @@ -83,6 +83,8 @@ struct pll_config { u32 aux2_output_mask; u32 aux2_output_mask; u32 early_output_mask; u32 early_output_mask; u32 config_ctl_val; u32 config_ctl_val; u32 config_ctl_hi_val; u32 config_ctl_hi1_val; }; }; void clk_pll_configure_sr(struct clk_pll *pll, struct regmap *regmap, void clk_pll_configure_sr(struct clk_pll *pll, struct regmap *regmap, Loading Loading
drivers/clk/qcom/clk-alpha-pll.c +472 −17 Original line number Original line Diff line number Diff line Loading @@ -22,6 +22,8 @@ #include "clk-alpha-pll.h" #include "clk-alpha-pll.h" #define PLL_MODE 0x00 #define PLL_MODE 0x00 #define PLL_STANDBY 0x0 #define PLL_RUN 0x1 # define PLL_OUTCTRL BIT(0) # define PLL_OUTCTRL BIT(0) # define PLL_BYPASSNL BIT(1) # define PLL_BYPASSNL BIT(1) # define PLL_RESET_N BIT(2) # define PLL_RESET_N BIT(2) Loading Loading @@ -51,25 +53,40 @@ #define PLL_TEST_CTL 0x1c #define PLL_TEST_CTL 0x1c #define PLL_TEST_CTL_U 0x20 #define PLL_TEST_CTL_U 0x20 #define PLL_STATUS 0x24 #define PLL_STATUS 0x24 #define PLL_UPDATE BIT(22) #define PLL_ACK_LATCH BIT(29) #define PLL_CALIBRATION_MASK (0x7<<3) #define PLL_CALIBRATION_CONTROL 2 #define PLL_HW_UPDATE_LOGIC_BYPASS BIT(23) #define ALPHA_16_BIT_PLL_RATE_MARGIN 500 /* /* * Even though 40 bits are present, use only 32 for ease of calculation. * Even though 40 bits are present, use only 32 for ease of calculation. */ */ #define ALPHA_REG_BITWIDTH 40 #define ALPHA_REG_BITWIDTH 40 #define ALPHA_BITWIDTH 32 #define ALPHA_BITWIDTH 32 #define FABIA_BITWIDTH 16 #define SUPPORTS_16BIT_ALPHA 16 #define FABIA_USER_CTL_LO 0xc #define FABIA_USER_CTL_LO 0xc #define FABIA_USER_CTL_HI 0x10 #define FABIA_USER_CTL_HI 0x10 #define FABIA_FRAC_VAL 0x38 #define FABIA_FRAC_VAL 0x38 #define FABIA_OPMODE 0x2c #define FABIA_OPMODE 0x2c #define FABIA_PLL_STANDBY 0x0 #define FABIA_PLL_RUN 0x1 #define FABIA_PLL_OUT_MASK 0x7 #define FABIA_PLL_OUT_MASK 0x7 #define FABIA_PLL_RATE_MARGIN 500 #define FABIA_PLL_ACK_LATCH BIT(29) #define FABIA_PLL_ACK_LATCH BIT(29) #define FABIA_PLL_UPDATE BIT(22) #define FABIA_PLL_UPDATE BIT(22) #define FABIA_PLL_HW_UPDATE_LOGIC_BYPASS BIT(23) #define TRION_PLL_CAL_VAL 0x44 #define TRION_PLL_CAL_L_VAL 0x8 #define TRION_PLL_USER_CTL 0xc #define TRION_PLL_USER_CTL_U 0x10 #define TRION_PLL_USER_CTL_U1 0x14 #define TRION_PLL_CONFIG_CTL_U 0x1c #define TRION_PLL_CONFIG_CTL_U1 0x20 #define TRION_PLL_OPMODE 0x38 #define TRION_PLL_ALPHA_VAL 0x40 #define TRION_PLL_OUT_MASK 0x7 #define TRION_PLL_ENABLE_STATE_READ BIT(4) #define to_clk_alpha_pll(_hw) container_of(to_clk_regmap(_hw), \ #define to_clk_alpha_pll(_hw) container_of(to_clk_regmap(_hw), \ struct clk_alpha_pll, clkr) struct clk_alpha_pll, clkr) Loading Loading @@ -121,6 +138,10 @@ static int wait_for_pll_offline(struct clk_alpha_pll *pll, u32 mask) return wait_for_pll(pll, mask, 0, "offline"); return wait_for_pll(pll, mask, 0, "offline"); } } static int wait_for_pll_latch_ack(struct clk_alpha_pll *pll, u32 mask) { return wait_for_pll(pll, mask, 0, "latch_ack"); } /* alpha pll with hwfsm support */ /* alpha pll with hwfsm support */ Loading Loading @@ -294,8 +315,8 @@ static unsigned long alpha_pll_calc_rate(const struct clk_alpha_pll *pll, { { int alpha_bw = ALPHA_BITWIDTH; int alpha_bw = ALPHA_BITWIDTH; if (pll->type == FABIA_PLL) if (pll->type == FABIA_PLL || pll->type == TRION_PLL) alpha_bw = FABIA_BITWIDTH; alpha_bw = SUPPORTS_16BIT_ALPHA; return (prate * l) + ((prate * a) >> alpha_bw); return (prate * l) + ((prate * a) >> alpha_bw); } } Loading Loading @@ -326,9 +347,9 @@ alpha_pll_round_rate(const struct clk_alpha_pll *pll, unsigned long rate, return rate; return rate; } } /* Fabia PLLs only have 16 bits to program the fractional divider */ /* Some PLLs only have 16 bits to program the fractional divider */ if (pll->type == FABIA_PLL) if (pll->type == FABIA_PLL || pll->type == TRION_PLL) alpha_bw = FABIA_BITWIDTH; alpha_bw = SUPPORTS_16BIT_ALPHA; /* Upper ALPHA_BITWIDTH bits of Alpha */ /* Upper ALPHA_BITWIDTH bits of Alpha */ quotient = remainder << alpha_bw; quotient = remainder << alpha_bw; Loading Loading @@ -415,7 +436,8 @@ static long clk_alpha_pll_round_rate(struct clk_hw *hw, unsigned long rate, unsigned long min_freq, max_freq; unsigned long min_freq, max_freq; rate = alpha_pll_round_rate(pll, rate, *prate, &l, &a); rate = alpha_pll_round_rate(pll, rate, *prate, &l, &a); if (pll->type == FABIA_PLL || alpha_pll_find_vco(pll, rate)) if (pll->type == FABIA_PLL || pll->type == TRION_PLL || alpha_pll_find_vco(pll, rate)) return rate; return rate; min_freq = pll->vco_table[0].min_freq; min_freq = pll->vco_table[0].min_freq; Loading Loading @@ -523,8 +545,8 @@ void clk_fabia_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, clk_fabia_pll_latch_input(pll, regmap); clk_fabia_pll_latch_input(pll, regmap); regmap_update_bits(regmap, pll->offset + PLL_MODE, regmap_update_bits(regmap, pll->offset + PLL_MODE, FABIA_PLL_HW_UPDATE_LOGIC_BYPASS, PLL_HW_UPDATE_LOGIC_BYPASS, FABIA_PLL_HW_UPDATE_LOGIC_BYPASS); PLL_HW_UPDATE_LOGIC_BYPASS); regmap_update_bits(regmap, pll->offset + PLL_MODE, regmap_update_bits(regmap, pll->offset + PLL_MODE, PLL_RESET_N, PLL_RESET_N); PLL_RESET_N, PLL_RESET_N); Loading Loading @@ -560,7 +582,7 @@ static int clk_fabia_pll_enable(struct clk_hw *hw) return ret; return ret; /* Set operation mode to STANDBY */ /* Set operation mode to STANDBY */ regmap_write(pll->clkr.regmap, off + FABIA_OPMODE, FABIA_PLL_STANDBY); regmap_write(pll->clkr.regmap, off + FABIA_OPMODE, PLL_STANDBY); /* PLL should be in STANDBY mode before continuing */ /* PLL should be in STANDBY mode before continuing */ mb(); mb(); Loading @@ -572,7 +594,7 @@ static int clk_fabia_pll_enable(struct clk_hw *hw) return ret; return ret; /* Set operation mode to RUN */ /* Set operation mode to RUN */ regmap_write(pll->clkr.regmap, off + FABIA_OPMODE, FABIA_PLL_RUN); regmap_write(pll->clkr.regmap, off + FABIA_OPMODE, PLL_RUN); ret = wait_for_pll_enable(pll, PLL_LOCK_DET); ret = wait_for_pll_enable(pll, PLL_LOCK_DET); if (ret) if (ret) Loading Loading @@ -624,7 +646,7 @@ static void clk_fabia_pll_disable(struct clk_hw *hw) return; return; /* Place the PLL mode in STANDBY */ /* Place the PLL mode in STANDBY */ regmap_write(pll->clkr.regmap, off + FABIA_OPMODE, FABIA_PLL_STANDBY); regmap_write(pll->clkr.regmap, off + FABIA_OPMODE, PLL_STANDBY); } } static unsigned long static unsigned long Loading Loading @@ -659,7 +681,7 @@ static int clk_fabia_pll_set_rate(struct clk_hw *hw, unsigned long rate, * Due to limited number of bits for fractional rate programming, the * Due to limited number of bits for fractional rate programming, the * rounded up rate could be marginally higher than the requested rate. * rounded up rate could be marginally higher than the requested rate. */ */ if (rrate > (rate + FABIA_PLL_RATE_MARGIN) || rrate < rate) { if (rrate > (rate + ALPHA_16_BIT_PLL_RATE_MARGIN) || rrate < rate) { pr_err("Call set rate on the PLL with rounded rates!\n"); pr_err("Call set rate on the PLL with rounded rates!\n"); return -EINVAL; return -EINVAL; } } Loading Loading @@ -879,3 +901,436 @@ const struct clk_ops clk_generic_pll_postdiv_ops = { .set_rate = clk_generic_pll_postdiv_set_rate, .set_rate = clk_generic_pll_postdiv_set_rate, }; }; EXPORT_SYMBOL_GPL(clk_generic_pll_postdiv_ops); EXPORT_SYMBOL_GPL(clk_generic_pll_postdiv_ops); static int trion_pll_is_enabled(struct clk_alpha_pll *pll, struct regmap *regmap) { u32 mode_val, opmode_val, off = pll->offset; int ret; ret = regmap_read(regmap, off + PLL_MODE, &mode_val); ret |= regmap_read(regmap, off + TRION_PLL_OPMODE, &opmode_val); if (ret) return 0; return ((opmode_val & PLL_RUN) && (mode_val & PLL_OUTCTRL)); } int clk_trion_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, const struct pll_config *config) { int ret = 0; if (trion_pll_is_enabled(pll, regmap)) { pr_debug("PLL is already enabled. Skipping configuration.\n"); /* * Set the PLL_HW_UPDATE_LOGIC_BYPASS bit to latch the input * before continuing. */ regmap_update_bits(regmap, pll->offset + PLL_MODE, PLL_HW_UPDATE_LOGIC_BYPASS, PLL_HW_UPDATE_LOGIC_BYPASS); pll->inited = true; return ret; } /* * Disable the PLL if it's already been initialized. Not doing so might * lead to the PLL running with the old frequency configuration. */ if (pll->inited) { ret = regmap_update_bits(regmap, pll->offset + PLL_MODE, PLL_RESET_N, 0); if (ret) return ret; } if (config->l) regmap_write(regmap, pll->offset + PLL_L_VAL, config->l); regmap_write(regmap, pll->offset + TRION_PLL_CAL_L_VAL, TRION_PLL_CAL_VAL); if (config->frac) regmap_write(regmap, pll->offset + TRION_PLL_ALPHA_VAL, config->frac); if (config->config_ctl_val) regmap_write(regmap, pll->offset + PLL_CONFIG_CTL, config->config_ctl_val); if (config->config_ctl_hi_val) regmap_write(regmap, pll->offset + TRION_PLL_CONFIG_CTL_U, config->config_ctl_hi_val); if (config->config_ctl_hi1_val) regmap_write(regmap, pll->offset + TRION_PLL_CONFIG_CTL_U1, config->config_ctl_hi1_val); if (config->post_div_mask) regmap_update_bits(regmap, pll->offset + TRION_PLL_USER_CTL, config->post_div_mask, config->post_div_val); /* Disable state read */ regmap_update_bits(regmap, pll->offset + TRION_PLL_USER_CTL_U, TRION_PLL_ENABLE_STATE_READ, 0); regmap_update_bits(regmap, pll->offset + PLL_MODE, PLL_HW_UPDATE_LOGIC_BYPASS, PLL_HW_UPDATE_LOGIC_BYPASS); /* Set calibration control to Automatic */ regmap_update_bits(regmap, pll->offset + TRION_PLL_USER_CTL_U, PLL_CALIBRATION_MASK, PLL_CALIBRATION_CONTROL); /* Disable PLL output */ ret = regmap_update_bits(regmap, pll->offset + PLL_MODE, PLL_OUTCTRL, 0); if (ret) return ret; /* Set operation mode to OFF */ regmap_write(regmap, pll->offset + TRION_PLL_OPMODE, PLL_STANDBY); /* PLL should be in OFF mode before continuing */ wmb(); /* Place the PLL in STANDBY mode */ ret = regmap_update_bits(regmap, pll->offset + PLL_MODE, PLL_RESET_N, PLL_RESET_N); if (ret) return ret; pll->inited = true; return ret; } static int clk_alpha_pll_latch_l_val(struct clk_alpha_pll *pll) { int ret; /* Latch the input to the PLL */ ret = regmap_update_bits(pll->clkr.regmap, pll->offset + PLL_MODE, PLL_UPDATE, PLL_UPDATE); if (ret) return ret; /* Wait for 2 reference cycle before checking ACK bit */ udelay(1); ret = wait_for_pll_latch_ack(pll, PLL_ACK_LATCH); if (ret) return ret; /* Return latch input to 0 */ ret = regmap_update_bits(pll->clkr.regmap, pll->offset + PLL_MODE, PLL_UPDATE, (u32)~PLL_UPDATE); if (ret) return ret; return 0; } static int clk_trion_pll_enable(struct clk_hw *hw) { int ret = 0; struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); u32 val, off = pll->offset; ret = regmap_read(pll->clkr.regmap, off + PLL_MODE, &val); if (ret) return ret; /* If in FSM mode, just vote for it */ if (val & PLL_VOTE_FSM_ENA) { ret = clk_enable_regmap(hw); if (ret) return ret; return wait_for_pll_enable(pll, PLL_ACTIVE_FLAG); } if (unlikely(!pll->inited)) { ret = clk_trion_pll_configure(pll, pll->clkr.regmap, pll->config); if (ret) { pr_err("Failed to configure %s\n", clk_hw_get_name(hw)); return ret; } } /* Skip If PLL is already running */ if (trion_pll_is_enabled(pll, pll->clkr.regmap)) return ret; /* Set operation mode to RUN */ regmap_write(pll->clkr.regmap, off + TRION_PLL_OPMODE, PLL_RUN); ret = wait_for_pll_enable(pll, PLL_LOCK_DET); if (ret) return ret; /* Enable PLL main output */ ret = regmap_update_bits(pll->clkr.regmap, off + TRION_PLL_USER_CTL, TRION_PLL_OUT_MASK, TRION_PLL_OUT_MASK); if (ret) return ret; /* Enable Global PLL outputs */ ret = regmap_update_bits(pll->clkr.regmap, off + PLL_MODE, PLL_OUTCTRL, PLL_OUTCTRL); if (ret) return ret; /* Ensure that the write above goes through before returning. */ mb(); return ret; } static void clk_trion_pll_disable(struct clk_hw *hw) { int ret; struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); u32 val, off = pll->offset; ret = regmap_read(pll->clkr.regmap, off + PLL_MODE, &val); if (ret) return; /* If in FSM mode, just unvote it */ if (val & PLL_VOTE_FSM_ENA) { clk_disable_regmap(hw); return; } /* Disable Global PLL outputs */ ret = regmap_update_bits(pll->clkr.regmap, off + PLL_MODE, PLL_OUTCTRL, 0); if (ret) return; /* Disable the main PLL output */ ret = regmap_update_bits(pll->clkr.regmap, off + TRION_PLL_USER_CTL, TRION_PLL_OUT_MASK, 0); if (ret) return; /* Place the PLL into STANDBY mode */ regmap_write(pll->clkr.regmap, off + TRION_PLL_OPMODE, PLL_STANDBY); regmap_update_bits(pll->clkr.regmap, off + PLL_MODE, PLL_RESET_N, PLL_RESET_N); } static unsigned long clk_trion_pll_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) { u32 l, frac = 0; u64 prate = parent_rate; struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); u32 off = pll->offset; regmap_read(pll->clkr.regmap, off + PLL_L_VAL, &l); regmap_read(pll->clkr.regmap, off + TRION_PLL_ALPHA_VAL, &frac); return alpha_pll_calc_rate(pll, prate, l, frac); } static int clk_trion_pll_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long prate) { struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); unsigned long rrate; bool is_enabled; int ret; u32 l, val, off = pll->offset; u64 a; rrate = alpha_pll_round_rate(pll, rate, prate, &l, &a); /* * Due to limited number of bits for fractional rate programming, the * rounded up rate could be marginally higher than the requested rate. */ if (rrate > (rate + ALPHA_16_BIT_PLL_RATE_MARGIN) || rrate < rate) { pr_err("Trion_pll: Call clk_set_rate with rounded rates!\n"); return -EINVAL; } is_enabled = clk_hw_is_enabled(hw); if (is_enabled) hw->init->ops->disable(hw); regmap_write(pll->clkr.regmap, off + PLL_L_VAL, l); regmap_write(pll->clkr.regmap, off + TRION_PLL_ALPHA_VAL, a); ret = regmap_read(pll->clkr.regmap, off + PLL_MODE, &val); if (ret) return ret; /* * If PLL is in Standby or RUN mode then only latch the L value * Else PLL is in OFF mode and just configure L register - as per * HPG no need to latch input. */ if (val & PLL_RESET_N) clk_alpha_pll_latch_l_val(pll); if (is_enabled) hw->init->ops->enable(hw); /* Wait for PLL output to stabilize */ udelay(100); return ret; } static int clk_trion_pll_is_enabled(struct clk_hw *hw) { struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); return trion_pll_is_enabled(pll, pll->clkr.regmap); } static void clk_trion_pll_list_registers(struct seq_file *f, struct clk_hw *hw) { struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); int size, i, val; static struct clk_register_data data[] = { {"PLL_MODE", 0x0}, {"PLL_L_VAL", 0x4}, {"PLL_USER_CTL", 0xc}, {"PLL_USER_CTL_U", 0x10}, {"PLL_USER_CTL_U1", 0x14}, {"PLL_CONFIG_CTL", 0x18}, {"PLL_CONFIG_CTL_U", 0x1c}, {"PLL_CONFIG_CTL_U1", 0x20}, {"PLL_OPMODE", 0x38}, }; static struct clk_register_data data1[] = { {"APSS_PLL_VOTE", 0x0}, }; size = ARRAY_SIZE(data); for (i = 0; i < size; i++) { regmap_read(pll->clkr.regmap, pll->offset + data[i].offset, &val); seq_printf(f, "%20s: 0x%.8x\n", data[i].name, val); } regmap_read(pll->clkr.regmap, pll->offset + data[0].offset, &val); if (val & PLL_VOTE_FSM_ENA) { regmap_read(pll->clkr.regmap, pll->clkr.enable_reg + data1[0].offset, &val); seq_printf(f, "%20s: 0x%.8x\n", data1[0].name, val); } } const struct clk_ops clk_trion_pll_ops = { .enable = clk_trion_pll_enable, .disable = clk_trion_pll_disable, .recalc_rate = clk_trion_pll_recalc_rate, .round_rate = clk_alpha_pll_round_rate, .set_rate = clk_trion_pll_set_rate, .is_enabled = clk_trion_pll_is_enabled, .list_registers = clk_trion_pll_list_registers, }; EXPORT_SYMBOL(clk_trion_pll_ops); const struct clk_ops clk_trion_fixed_pll_ops = { .enable = clk_trion_pll_enable, .disable = clk_trion_pll_disable, .recalc_rate = clk_trion_pll_recalc_rate, .round_rate = clk_alpha_pll_round_rate, .is_enabled = clk_trion_pll_is_enabled, .list_registers = clk_trion_pll_list_registers, }; EXPORT_SYMBOL(clk_trion_fixed_pll_ops); static unsigned long clk_trion_pll_postdiv_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) { struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw); u32 i, cal_div = 1, val; if (!pll->post_div_table) { pr_err("Missing the post_div_table for the PLL\n"); return -EINVAL; } regmap_read(pll->clkr.regmap, pll->offset + TRION_PLL_USER_CTL, &val); val >>= pll->post_div_shift; val &= PLL_POST_DIV_MASK; for (i = 0; i < pll->num_post_div; i++) { if (pll->post_div_table[i].val == val) { cal_div = pll->post_div_table[i].div; break; } } return (parent_rate / cal_div); } static long clk_trion_pll_postdiv_round_rate(struct clk_hw *hw, unsigned long rate, unsigned long *prate) { struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw); if (!pll->post_div_table) return -EINVAL; return divider_round_rate(hw, rate, prate, pll->post_div_table, pll->width, CLK_DIVIDER_ROUND_CLOSEST); } static int clk_trion_pll_postdiv_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate) { struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw); int i, val = 0, cal_div, ret; /* * If the PLL is in FSM mode, then treat the set_rate callback * as a no-operation. */ ret = regmap_read(pll->clkr.regmap, pll->offset + PLL_MODE, &val); if (ret) return ret; if (val & PLL_VOTE_FSM_ENA) return 0; if (!pll->post_div_table) { pr_err("Missing the post_div_table for the PLL\n"); return -EINVAL; } cal_div = DIV_ROUND_UP_ULL((u64)parent_rate, rate); for (i = 0; i < pll->num_post_div; i++) { if (pll->post_div_table[i].div == cal_div) { val = pll->post_div_table[i].val; break; } } return regmap_update_bits(pll->clkr.regmap, pll->offset + TRION_PLL_USER_CTL, PLL_POST_DIV_MASK << pll->post_div_shift, val << pll->post_div_shift); } const struct clk_ops clk_trion_pll_postdiv_ops = { .recalc_rate = clk_trion_pll_postdiv_recalc_rate, .round_rate = clk_trion_pll_postdiv_round_rate, .set_rate = clk_trion_pll_postdiv_set_rate, }; EXPORT_SYMBOL(clk_trion_pll_postdiv_ops);
drivers/clk/qcom/clk-alpha-pll.h +8 −2 Original line number Original line Diff line number Diff line /* /* * Copyright (c) 2015-2016, The Linux Foundation. All rights reserved. * Copyright (c) 2015-2017, The Linux Foundation. All rights reserved. * * * This software is licensed under the terms of the GNU General Public * This software is licensed under the terms of the GNU General Public * License version 2, as published by the Free Software Foundation, and * License version 2, as published by the Free Software Foundation, and Loading Loading @@ -27,6 +27,7 @@ struct pll_vco { enum pll_type { enum pll_type { ALPHA_PLL, ALPHA_PLL, FABIA_PLL, FABIA_PLL, TRION_PLL, }; }; /** /** Loading @@ -35,7 +36,7 @@ enum pll_type { * @inited: flag that's set when the PLL is initialized * @inited: flag that's set when the PLL is initialized * @vco_table: array of VCO settings * @vco_table: array of VCO settings * @clkr: regmap clock handle * @clkr: regmap clock handle * @is_fabia: Set if the PLL type is FABIA * @pll_type: Specify the type of PLL */ */ struct clk_alpha_pll { struct clk_alpha_pll { u32 offset; u32 offset; Loading Loading @@ -79,10 +80,15 @@ extern const struct clk_ops clk_alpha_pll_postdiv_ops; extern const struct clk_ops clk_fabia_pll_ops; extern const struct clk_ops clk_fabia_pll_ops; extern const struct clk_ops clk_fabia_fixed_pll_ops; extern const struct clk_ops clk_fabia_fixed_pll_ops; extern const struct clk_ops clk_generic_pll_postdiv_ops; extern const struct clk_ops clk_generic_pll_postdiv_ops; extern const struct clk_ops clk_trion_pll_ops; extern const struct clk_ops clk_trion_fixed_pll_ops; extern const struct clk_ops clk_trion_pll_postdiv_ops; void clk_alpha_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, void clk_alpha_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, const struct pll_config *config); const struct pll_config *config); void clk_fabia_pll_configure(struct clk_alpha_pll *pll, void clk_fabia_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, const struct pll_config *config); struct regmap *regmap, const struct pll_config *config); int clk_trion_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, const struct pll_config *config); #endif #endif
drivers/clk/qcom/clk-pll.h +3 −1 Original line number Original line Diff line number Diff line /* /* * Copyright (c) 2013, 2016, The Linux Foundation. All rights reserved. * Copyright (c) 2013, 2016-2017, The Linux Foundation. All rights reserved. * * * This software is licensed under the terms of the GNU General Public * This software is licensed under the terms of the GNU General Public * License version 2, as published by the Free Software Foundation, and * License version 2, as published by the Free Software Foundation, and Loading Loading @@ -83,6 +83,8 @@ struct pll_config { u32 aux2_output_mask; u32 aux2_output_mask; u32 early_output_mask; u32 early_output_mask; u32 config_ctl_val; u32 config_ctl_val; u32 config_ctl_hi_val; u32 config_ctl_hi1_val; }; }; void clk_pll_configure_sr(struct clk_pll *pll, struct regmap *regmap, void clk_pll_configure_sr(struct clk_pll *pll, struct regmap *regmap, Loading
