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Commit 85a0e753 authored by Ondrej Zary's avatar Ondrej Zary Committed by Rafael J. Wysocki
Browse files

PM / x86: Save/restore MISC_ENABLE register 

Save/restore MISC_ENABLE register on suspend/resume.
This fixes OOPS (invalid opcode) on resume from STR on Asus P4P800-VM,
which wakes up with MWAIT disabled.

Fixes https://bugzilla.kernel.org/show_bug.cgi?id=15385



Signed-off-by: default avatarOndrej Zary <linux@rainbow-software.org>
Tested-by: default avatarAlan Stern <stern@rowland.harvard.edu>
Acked-by: default avatarH. Peter Anvin <hpa@linux.intel.com>
Signed-off-by: default avatarRafael J. Wysocki <rjw@sisk.pl>
parent 386f40c8

arch/x86/include/asm/suspend_32.h

+2 −0
Original line number Diff line number Diff line
@@ -15,6 +15,8 @@ static inline int arch_prepare_suspend(void) { return 0; } 
struct saved_context {

	u16 es, fs, gs, ss;

	unsigned long cr0, cr2, cr3, cr4;

	u64 misc_enable;

	bool misc_enable_saved;

	struct desc_ptr gdt;

	struct desc_ptr idt;

	u16 ldt;

arch/x86/include/asm/suspend_64.h

+2 −0
Original line number Diff line number Diff line
@@ -27,6 +27,8 @@ struct saved_context { 
	u16 ds, es, fs, gs, ss;

	unsigned long gs_base, gs_kernel_base, fs_base;

	unsigned long cr0, cr2, cr3, cr4, cr8;

	u64 misc_enable;

	bool misc_enable_saved;

	unsigned long efer;

	u16 gdt_pad;

	u16 gdt_limit;

arch/x86/power/cpu.c

+4 −0
Original line number Diff line number Diff line
@@ -105,6 +105,8 @@ static void __save_processor_state(struct saved_context *ctxt) 
	ctxt->cr4 = read_cr4();

	ctxt->cr8 = read_cr8();

#endif

	ctxt->misc_enable_saved = !rdmsrl_safe(MSR_IA32_MISC_ENABLE,

					       &ctxt->misc_enable);

}



/* Needed by apm.c */
@@ -152,6 +154,8 @@ static void fix_processor_context(void) 
 */

static void __restore_processor_state(struct saved_context *ctxt)

{

	if (ctxt->misc_enable_saved)

		wrmsrl(MSR_IA32_MISC_ENABLE, ctxt->misc_enable);

	/*

	 * control registers

	 */