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Commit 8567af02 authored by Carter Cooper's avatar Carter Cooper
Browse files

msm: kgsl: Move spin idle debug print into adreno base code 



This code is used by A5XX and A6XX. Make it general and expose
to all of adreno.

Change-Id: I5dcff7a70828417f53205fafdb3c22147ebb2eaf
Signed-off-by: default avatarCarter Cooper <ccooper@codeaurora.org>
parent c0b75812

drivers/gpu/msm/adreno.c

+28 −0
Original line number Diff line number Diff line
@@ -2325,6 +2325,34 @@ bool adreno_isidle(struct kgsl_device *device) 
	return adreno_hw_isidle(adreno_dev);

}



/* Print some key registers if a spin-for-idle times out */

void adreno_spin_idle_debug(struct adreno_device *adreno_dev,

		const char *str)

{

	struct kgsl_device *device = &adreno_dev->dev;

	unsigned int rptr, wptr;

	unsigned int status, status3, intstatus;

	unsigned int hwfault;



	dev_err(device->dev, str);



	adreno_readreg(adreno_dev, ADRENO_REG_CP_RB_RPTR, &rptr);

	adreno_readreg(adreno_dev, ADRENO_REG_CP_RB_WPTR, &wptr);



	adreno_readreg(adreno_dev, ADRENO_REG_RBBM_STATUS, &status);

	adreno_readreg(adreno_dev, ADRENO_REG_RBBM_STATUS3, &status3);

	adreno_readreg(adreno_dev, ADRENO_REG_RBBM_INT_0_STATUS, &intstatus);

	adreno_readreg(adreno_dev, ADRENO_REG_CP_HW_FAULT, &hwfault);



	dev_err(device->dev,

		"rb=%d pos=%X/%X rbbm_status=%8.8X/%8.8X int_0_status=%8.8X\n",

		adreno_dev->cur_rb->id, rptr, wptr, status, status3, intstatus);



	dev_err(device->dev, " hwfault=%8.8X\n", hwfault);



	kgsl_device_snapshot(device, NULL);

}



/**

 * adreno_spin_idle() - Spin wait for the GPU to idle

 * @adreno_dev: Pointer to an adreno device

drivers/gpu/msm/adreno.h

+1 −0
Original line number Diff line number Diff line
@@ -951,6 +951,7 @@ long adreno_ioctl_helper(struct kgsl_device_private *dev_priv, 
		unsigned int cmd, unsigned long arg,

		const struct kgsl_ioctl *cmds, int len);



void adreno_spin_idle_debug(struct adreno_device *adreno_dev, const char *str);

int adreno_spin_idle(struct adreno_device *device, unsigned int timeout);

int adreno_idle(struct kgsl_device *device);

bool adreno_isidle(struct kgsl_device *device);

drivers/gpu/msm/adreno_a5xx.c

+6 −33
Original line number Diff line number Diff line
@@ -82,34 +82,6 @@ static int a5xx_gpmu_init(struct adreno_device *adreno_dev); 
#define A530_QFPROM_RAW_PTE_ROW0_MSB 0x134

#define A530_QFPROM_RAW_PTE_ROW2_MSB 0x144



/* Print some key registers if a spin-for-idle times out */

static void spin_idle_debug(struct kgsl_device *device,

		const char *str)

{

	struct adreno_device *adreno_dev = ADRENO_DEVICE(device);

	unsigned int rptr, wptr;

	unsigned int status, status3, intstatus;

	unsigned int hwfault;



	dev_err(device->dev, str);



	adreno_readreg(adreno_dev, ADRENO_REG_CP_RB_RPTR, &rptr);

	adreno_readreg(adreno_dev, ADRENO_REG_CP_RB_WPTR, &wptr);



	kgsl_regread(device, A5XX_RBBM_STATUS, &status);

	kgsl_regread(device, A5XX_RBBM_STATUS3, &status3);

	kgsl_regread(device, A5XX_RBBM_INT_0_STATUS, &intstatus);

	kgsl_regread(device, A5XX_CP_HW_FAULT, &hwfault);



	dev_err(device->dev,

		"rb=%d pos=%X/%X rbbm_status=%8.8X/%8.8X int_0_status=%8.8X\n",

		adreno_dev->cur_rb->id, rptr, wptr, status, status3, intstatus);



	dev_err(device->dev, " hwfault=%8.8X\n", hwfault);



	kgsl_device_snapshot(device, NULL);

}



static void a530_efuse_leakage(struct adreno_device *adreno_dev)

{

	struct kgsl_device *device = KGSL_DEVICE(adreno_dev);
@@ -752,7 +724,7 @@ static int _gpmu_send_init_cmds(struct adreno_device *adreno_dev) 


	ret = adreno_ringbuffer_submit_spin(rb, NULL, 2000);

	if (ret != 0)

		spin_idle_debug(&adreno_dev->dev,

		adreno_spin_idle_debug(adreno_dev,

				"gpmu initialization failed to idle\n");



	return ret;
@@ -2153,7 +2125,7 @@ static int a5xx_post_start(struct adreno_device *adreno_dev) 


	ret = adreno_ringbuffer_submit_spin(rb, NULL, 2000);

	if (ret)

		spin_idle_debug(KGSL_DEVICE(adreno_dev),

		adreno_spin_idle_debug(adreno_dev,

				"hw initialization failed to idle\n");



	return ret;
@@ -2194,7 +2166,7 @@ static int a5xx_switch_to_unsecure_mode(struct adreno_device *adreno_dev, 


	ret = adreno_ringbuffer_submit_spin(rb, NULL, 2000);

	if (ret)

		spin_idle_debug(KGSL_DEVICE(adreno_dev),

		adreno_spin_idle_debug(adreno_dev,

				"Switch to unsecure failed to idle\n");



	return ret;
@@ -2379,7 +2351,7 @@ static int a5xx_critical_packet_submit(struct adreno_device *adreno_dev, 


	ret = adreno_ringbuffer_submit_spin(rb, NULL, 20);

	if (ret)

		spin_idle_debug(KGSL_DEVICE(adreno_dev),

		adreno_spin_idle_debug(adreno_dev,

			"Critical packet submission failed to idle\n");



	return ret;
@@ -2410,7 +2382,7 @@ static int a5xx_send_me_init(struct adreno_device *adreno_dev, 


	ret = adreno_ringbuffer_submit_spin(rb, NULL, 2000);

	if (ret)

		spin_idle_debug(KGSL_DEVICE(adreno_dev),

		adreno_spin_idle_debug(adreno_dev,

				"CP initialization failed to idle\n");



	return ret;
@@ -3025,6 +2997,7 @@ static unsigned int a5xx_register_offsets[ADRENO_REG_REGISTER_MAX] = { 
	ADRENO_REG_DEFINE(ADRENO_REG_CP_MEQ_ADDR, A5XX_CP_MEQ_DBG_ADDR),

	ADRENO_REG_DEFINE(ADRENO_REG_CP_MEQ_DATA, A5XX_CP_MEQ_DBG_DATA),

	ADRENO_REG_DEFINE(ADRENO_REG_CP_PROTECT_REG_0, A5XX_CP_PROTECT_REG_0),

	ADRENO_REG_DEFINE(ADRENO_REG_CP_HW_FAULT, A5XX_CP_HW_FAULT),

	ADRENO_REG_DEFINE(ADRENO_REG_CP_PREEMPT, A5XX_CP_CONTEXT_SWITCH_CNTL),

	ADRENO_REG_DEFINE(ADRENO_REG_CP_PREEMPT_DEBUG, ADRENO_REG_SKIP),

	ADRENO_REG_DEFINE(ADRENO_REG_CP_PREEMPT_DISABLE, ADRENO_REG_SKIP),

drivers/gpu/msm/adreno_a6xx.c

+2 −25
Original line number Diff line number Diff line
@@ -91,30 +91,6 @@ static struct a6xx_protected_regs { 
	{ 0xA630, 0x0, 1 },

};



/* Print some key registers if a spin-for-idle times out */

static void spin_idle_debug(struct kgsl_device *device,

		const char *str)

{

	unsigned int rptr, wptr;

	unsigned int status, status3, intstatus;

	unsigned int hwfault;



	dev_err(device->dev, str);



	kgsl_regread(device, A6XX_CP_RB_RPTR, &rptr);

	kgsl_regread(device, A6XX_CP_RB_WPTR, &wptr);



	kgsl_regread(device, A6XX_RBBM_STATUS, &status);

	kgsl_regread(device, A6XX_RBBM_STATUS3, &status3);

	kgsl_regread(device, A6XX_RBBM_INT_0_STATUS, &intstatus);

	kgsl_regread(device, A6XX_CP_HW_FAULT, &hwfault);



	dev_err(device->dev,

		" rb=%X/%X rbbm_status=%8.8X/%8.8X int_0_status=%8.8X\n",

		rptr, wptr, status, status3, intstatus);

	dev_err(device->dev, " hwfault=%8.8X\n", hwfault);

}



static void a6xx_platform_setup(struct adreno_device *adreno_dev)

{

	uint64_t addr;
@@ -415,7 +391,7 @@ static int a6xx_send_cp_init(struct adreno_device *adreno_dev, 


	ret = adreno_ringbuffer_submit_spin(rb, NULL, 2000);

	if (ret)

		spin_idle_debug(KGSL_DEVICE(adreno_dev),

		adreno_spin_idle_debug(adreno_dev,

				"CP initialization failed to idle\n");



	return ret;
@@ -1558,6 +1534,7 @@ static unsigned int a6xx_register_offsets[ADRENO_REG_REGISTER_MAX] = { 
	ADRENO_REG_DEFINE(ADRENO_REG_CP_RB_WPTR, A6XX_CP_RB_WPTR),

	ADRENO_REG_DEFINE(ADRENO_REG_CP_RB_CNTL, A6XX_CP_RB_CNTL),

	ADRENO_REG_DEFINE(ADRENO_REG_CP_CNTL, A6XX_CP_MISC_CNTL),

	ADRENO_REG_DEFINE(ADRENO_REG_CP_HW_FAULT, A6XX_CP_HW_FAULT),

	ADRENO_REG_DEFINE(ADRENO_REG_RBBM_STATUS, A6XX_RBBM_STATUS),

	ADRENO_REG_DEFINE(ADRENO_REG_RBBM_STATUS3, A6XX_RBBM_STATUS3),