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Commit 84fd4f4e authored by Rafael Barbalho's avatar Rafael Barbalho Committed by Daniel Vetter
Browse files

drm/i915/chv: Add CHV display support 



Add support for the third pipe in cherrview

v2: Don't use spaces for indentation (Jani)
    Wrap long lines

Reviewed-by: default avatarImre Deak <imre.deak@intel.com>
Signed-off-by: default avatarRafael Barbalho <rafael.barbalho@intel.com>
[vsyrjala: slightly massaged the patch]
Signed-off-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent e0d34ce7

drivers/gpu/drm/i915/i915_drv.c

+12 −0
Original line number Diff line number Diff line
@@ -49,6 +49,17 @@ static struct drm_driver driver; 
	.dpll_md_offsets = { DPLL_A_MD_OFFSET, DPLL_B_MD_OFFSET }, \

	.palette_offsets = { PALETTE_A_OFFSET, PALETTE_B_OFFSET }



#define GEN_CHV_PIPEOFFSETS \

	.pipe_offsets = { PIPE_A_OFFSET, PIPE_B_OFFSET, \

			  CHV_PIPE_C_OFFSET }, \

	.trans_offsets = { TRANSCODER_A_OFFSET, TRANSCODER_B_OFFSET, \

			   CHV_TRANSCODER_C_OFFSET, }, \

	.dpll_offsets = { DPLL_A_OFFSET, DPLL_B_OFFSET, \

			  CHV_DPLL_C_OFFSET }, \

	.dpll_md_offsets = { DPLL_A_MD_OFFSET, DPLL_B_MD_OFFSET, \

			     CHV_DPLL_C_MD_OFFSET }, \

	.palette_offsets = { PALETTE_A_OFFSET, PALETTE_B_OFFSET, \

			     CHV_PALETTE_C_OFFSET }



static const struct intel_device_info intel_i830_info = {

	.gen = 2, .is_mobile = 1, .cursor_needs_physical = 1, .num_pipes = 2,
@@ -306,6 +317,7 @@ static const struct intel_device_info intel_cherryview_info = { 
	.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,

	.is_valleyview = 1,

	.display_mmio_offset = VLV_DISPLAY_BASE,

	GEN_CHV_PIPEOFFSETS,

};



/*

drivers/gpu/drm/i915/i915_reg.h

+8 −3
Original line number Diff line number Diff line
@@ -1452,6 +1452,7 @@ enum punit_power_well { 
 */

#define DPLL_A_OFFSET 0x6014

#define DPLL_B_OFFSET 0x6018

#define CHV_DPLL_C_OFFSET 0x6030

#define DPLL(pipe) (dev_priv->info.dpll_offsets[pipe] + \

		    dev_priv->info.display_mmio_offset)
@@ -1543,6 +1544,7 @@ enum punit_power_well { 


#define DPLL_A_MD_OFFSET 0x601c /* 965+ only */

#define DPLL_B_MD_OFFSET 0x6020 /* 965+ only */

#define CHV_DPLL_C_MD_OFFSET 0x603c

#define DPLL_MD(pipe) (dev_priv->info.dpll_md_offsets[pipe] + \

		       dev_priv->info.display_mmio_offset)
@@ -1739,6 +1741,7 @@ enum punit_power_well { 
 */

#define PALETTE_A_OFFSET 0xa000

#define PALETTE_B_OFFSET 0xa800

#define CHV_PALETTE_C_OFFSET 0xc000

#define PALETTE(pipe) (dev_priv->info.palette_offsets[pipe] + \

		       dev_priv->info.display_mmio_offset)
@@ -2228,6 +2231,7 @@ enum punit_power_well { 
#define TRANSCODER_A_OFFSET 0x60000

#define TRANSCODER_B_OFFSET 0x61000

#define TRANSCODER_C_OFFSET 0x62000

#define CHV_TRANSCODER_C_OFFSET 0x63000

#define TRANSCODER_EDP_OFFSET 0x6f000



#define _TRANSCODER2(pipe, reg) (dev_priv->info.trans_offsets[(pipe)] - \
@@ -3559,6 +3563,7 @@ enum punit_power_well { 
#define PIPE_A_OFFSET		0x70000

#define PIPE_B_OFFSET		0x71000

#define PIPE_C_OFFSET		0x72000

#define CHV_PIPE_C_OFFSET	0x74000

/*

 * There's actually no pipe EDP. Some pipe registers have

 * simply shifted from the pipe to the transcoder, while