Merge "drm/msm: exit from mode-2 if mdss gdsc power collapse fail" (84822319) · Commits · e / devices / android_kernel_fairphone_FP3

drivers/gpu/drm/msm/sde_rsc_hw.c

+71 −81

Original line number	Original line	Diff line number	Diff line
	@@ -294,7 +294,70 @@ static int rsc_hw_solver_init(struct sde_rsc_priv *rsc)
	return 0;		return 0;
	}		}

	int sde_rsc_mode2_entry(struct sde_rsc_priv *rsc)		static int sde_rsc_mode2_exit(struct sde_rsc_priv *rsc,
			enum sde_rsc_state state)
			{
			int rc = -EBUSY;
			int count, reg;

			rsc_event_trigger(rsc, SDE_RSC_EVENT_PRE_CORE_RESTORE);

			/**
			* force busy and idle during clk & video mode state because it
			* is trying to entry in mode-2 without turning on the vysnc.
			*/
			if ((state == SDE_RSC_VID_STATE) \|\| (state == SDE_RSC_CLK_STATE)) {
			reg = dss_reg_r(&rsc->wrapper_io,
			SDE_RSCC_WRAPPER_OVERRIDE_CTRL, rsc->debug_mode);
			reg &= ~(BIT(8) \| BIT(0));
			dss_reg_w(&rsc->wrapper_io, SDE_RSCC_WRAPPER_OVERRIDE_CTRL,
			reg, rsc->debug_mode);
			}

			// needs review with HPG sequence
			dss_reg_w(&rsc->wrapper_io, SDE_RSCC_F1_QTMR_V1_CNTP_CVAL_LO,
			0x0, rsc->debug_mode);
			dss_reg_w(&rsc->wrapper_io, SDE_RSCC_F1_QTMR_V1_CNTP_CVAL_HI,
			0x0, rsc->debug_mode);

			reg = dss_reg_r(&rsc->wrapper_io, SDE_RSCC_WRAPPER_CTRL,
			rsc->debug_mode);
			reg &= ~BIT(3);
			dss_reg_w(&rsc->wrapper_io, SDE_RSCC_WRAPPER_CTRL,
			reg, rsc->debug_mode);

			reg = dss_reg_r(&rsc->wrapper_io, SDE_RSCC_SPARE_PWR_EVENT,
			rsc->debug_mode);
			reg \|= BIT(13);
			dss_reg_w(&rsc->wrapper_io, SDE_RSCC_SPARE_PWR_EVENT,
			reg, rsc->debug_mode);

			/* make sure that mode-2 exit before wait*/
			wmb();

			/* check for sequence running status before exiting */
			for (count = MAX_CHECK_LOOPS; count > 0; count--) {
			if (regulator_is_enabled(rsc->fs)) {
			rc = 0;
			break;
			}
			usleep_range(10, 100);
			}

			reg = dss_reg_r(&rsc->wrapper_io, SDE_RSCC_SPARE_PWR_EVENT,
			rsc->debug_mode);
			reg &= ~BIT(13);
			dss_reg_w(&rsc->wrapper_io, SDE_RSCC_SPARE_PWR_EVENT,
			reg, rsc->debug_mode);
			if (rc)
			pr_err("vdd reg is not enabled yet\n");

			rsc_event_trigger(rsc, SDE_RSC_EVENT_POST_CORE_RESTORE);

			return rc;
			}

			static int sde_rsc_mode2_entry(struct sde_rsc_priv *rsc)
	{		{
	int rc;		int rc;
	int count, wrapper_status;		int count, wrapper_status;
	@@ -309,8 +372,6 @@ int sde_rsc_mode2_entry(struct sde_rsc_priv *rsc)
	return rc;		return rc;
	}		}

	rc = -EBUSY;

	rsc_event_trigger(rsc, SDE_RSC_EVENT_PRE_CORE_PC);		rsc_event_trigger(rsc, SDE_RSC_EVENT_PRE_CORE_PC);

	/* update qtimers to high during clk & video mode state */		/* update qtimers to high during clk & video mode state */
	@@ -345,20 +406,7 @@ int sde_rsc_mode2_entry(struct sde_rsc_priv *rsc)
	/* make sure that mode-2 is triggered before wait*/		/* make sure that mode-2 is triggered before wait*/
	wmb();		wmb();

	/* check for sequence running status before exiting */		rc = -EBUSY;
	for (count = MAX_CHECK_LOOPS; count > 0; count--) {
	if (!regulator_is_enabled(rsc->fs)) {
	rc = 0;
	break;
	}
	usleep_range(1, 2);
	}

	if (rc) {
	pr_err("vdd fs is still enabled\n");
	goto end;
	} else {
	rc = -EINVAL;
	/* this wait is required to turn off the rscc clocks */		/* this wait is required to turn off the rscc clocks */
	for (count = MAX_CHECK_LOOPS; count > 0; count--) {		for (count = MAX_CHECK_LOOPS; count > 0; count--) {
	reg = dss_reg_r(&rsc->wrapper_io,		reg = dss_reg_r(&rsc->wrapper_io,
	@@ -369,6 +417,10 @@ int sde_rsc_mode2_entry(struct sde_rsc_priv *rsc)
	}		}
	usleep_range(1, 2);		usleep_range(1, 2);
	}		}

			if (rc) {
			pr_err("mdss gdsc power down failed rc:%d\n", rc);
			goto end;
	}		}

	if ((rsc->current_state == SDE_RSC_VID_STATE) \|\|		if ((rsc->current_state == SDE_RSC_VID_STATE) \|\|
	@@ -383,69 +435,7 @@ int sde_rsc_mode2_entry(struct sde_rsc_priv *rsc)
	return 0;		return 0;

	end:		end:
	rsc_event_trigger(rsc, SDE_RSC_EVENT_POST_CORE_RESTORE);		sde_rsc_mode2_exit(rsc, rsc->current_state);

	return rc;
	}

	int sde_rsc_mode2_exit(struct sde_rsc_priv *rsc, enum sde_rsc_state state)
	{
	int rc = -EBUSY;
	int count, reg;

	rsc_event_trigger(rsc, SDE_RSC_EVENT_PRE_CORE_RESTORE);

	/**
	* force busy and idle during clk & video mode state because it
	* is trying to entry in mode-2 without turning on the vysnc.
	*/
	if ((state == SDE_RSC_VID_STATE) \|\| (state == SDE_RSC_CLK_STATE)) {
	reg = dss_reg_r(&rsc->wrapper_io,
	SDE_RSCC_WRAPPER_OVERRIDE_CTRL, rsc->debug_mode);
	reg &= ~(BIT(8) \| BIT(0));
	dss_reg_w(&rsc->wrapper_io, SDE_RSCC_WRAPPER_OVERRIDE_CTRL,
	reg, rsc->debug_mode);
	}

	// needs review with HPG sequence
	dss_reg_w(&rsc->wrapper_io, SDE_RSCC_F1_QTMR_V1_CNTP_CVAL_LO,
	0x0, rsc->debug_mode);
	dss_reg_w(&rsc->wrapper_io, SDE_RSCC_F1_QTMR_V1_CNTP_CVAL_HI,
	0x0, rsc->debug_mode);

	reg = dss_reg_r(&rsc->wrapper_io, SDE_RSCC_WRAPPER_CTRL,
	rsc->debug_mode);
	reg &= ~BIT(3);
	dss_reg_w(&rsc->wrapper_io, SDE_RSCC_WRAPPER_CTRL,
	reg, rsc->debug_mode);

	reg = dss_reg_r(&rsc->wrapper_io, SDE_RSCC_SPARE_PWR_EVENT,
	rsc->debug_mode);
	reg \|= BIT(13);
	dss_reg_w(&rsc->wrapper_io, SDE_RSCC_SPARE_PWR_EVENT,
	reg, rsc->debug_mode);

	/* make sure that mode-2 exit before wait*/
	wmb();

	/* check for sequence running status before exiting */
	for (count = MAX_CHECK_LOOPS; count > 0; count--) {
	if (regulator_is_enabled(rsc->fs)) {
	rc = 0;
	break;
	}
	usleep_range(10, 100);
	}

	reg = dss_reg_r(&rsc->wrapper_io, SDE_RSCC_SPARE_PWR_EVENT,
	rsc->debug_mode);
	reg &= ~BIT(13);
	dss_reg_w(&rsc->wrapper_io, SDE_RSCC_SPARE_PWR_EVENT,
	reg, rsc->debug_mode);
	if (rc)
	pr_err("vdd reg is not enabled yet\n");

	rsc_event_trigger(rsc, SDE_RSC_EVENT_POST_CORE_RESTORE);

	return rc;		return rc;
	}		}