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Commit 847e8792 authored by Ulrich Hecht's avatar Ulrich Hecht Committed by Geert Uytterhoeven
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clk: renesas: r8a7795: add PWM clock 



Signed-off-by: default avatarUlrich Hecht <ulrich.hecht+renesas@gmail.com>
Signed-off-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
parent f55532a0

drivers/clk/renesas/r8a7795-cpg-mssr.c

+1 −0
Original line number Original line Diff line number Diff line
@@ -148,6 +148,7 @@ static const struct mssr_mod_clk r8a7795_mod_clks[] __initconst = { 
	DEF_MOD("hscif2",		 518,	R8A7795_CLK_S3D1),

	DEF_MOD("hscif2",		 518,	R8A7795_CLK_S3D1),

	DEF_MOD("hscif1",		 519,	R8A7795_CLK_S3D1),

	DEF_MOD("hscif1",		 519,	R8A7795_CLK_S3D1),

	DEF_MOD("hscif0",		 520,	R8A7795_CLK_S3D1),

	DEF_MOD("hscif0",		 520,	R8A7795_CLK_S3D1),

	DEF_MOD("pwm",			 523,	R8A7795_CLK_S3D4),

	DEF_MOD("fcpvd3",		 600,	R8A7795_CLK_S2D1),

	DEF_MOD("fcpvd3",		 600,	R8A7795_CLK_S2D1),

	DEF_MOD("fcpvd2",		 601,	R8A7795_CLK_S2D1),

	DEF_MOD("fcpvd2",		 601,	R8A7795_CLK_S2D1),

	DEF_MOD("fcpvd1",		 602,	R8A7795_CLK_S2D1),

	DEF_MOD("fcpvd1",		 602,	R8A7795_CLK_S2D1),