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Commit 8467ca01 authored by Markos Chandras's avatar Markos Chandras
Browse files

MIPS: Emulate the new MIPS R6 branch compact (BC) instruction 



MIPS R6 uses the <R6 LWC2 opcode for the new BC instruction.

Signed-off-by: default avatarMarkos Chandras <markos.chandras@imgtec.com>
parent f1b44067

arch/mips/include/uapi/asm/inst.h

+1 −1
Original line number Diff line number Diff line
@@ -31,7 +31,7 @@ enum major_op { 
	lbu_op, lhu_op, lwr_op, lwu_op,

	sb_op, sh_op, swl_op, sw_op,

	sdl_op, sdr_op, swr_op, cache_op,

	ll_op, lwc1_op, lwc2_op, pref_op,

	ll_op, lwc1_op, lwc2_op, bc6_op = lwc2_op, pref_op,

	lld_op, ldc1_op, ldc2_op, ld_op,

	sc_op, swc1_op, swc2_op, major_3b_op,

	scd_op, sdc1_op, sdc2_op, sd_op

arch/mips/kernel/branch.c

+9 −0
Original line number Diff line number Diff line
@@ -780,6 +780,15 @@ int __compute_return_epc_for_insn(struct pt_regs *regs, 
			epc += 8;

		regs->cp0_epc = epc;

		break;

#else

	case bc6_op:

		/* Only valid for MIPS R6 */

		if (!cpu_has_mips_r6) {

			ret = -SIGILL;

			break;

		}

		regs->cp0_epc += 8;

		break;

#endif

	}

arch/mips/math-emu/cp1emu.c

+13 −0
Original line number Diff line number Diff line
@@ -648,6 +648,19 @@ static int isBranchInstr(struct pt_regs *regs, struct mm_decoded_insn dec_insn, 
		else

			*contpc = regs->cp0_epc + 8;

		return 1;

#else

	case bc6_op:

		/*

		 * Only valid for MIPS R6 but we can still end up

		 * here from a broken userland so just tell emulator

		 * this is not a branch and let it break later on.

		 */

		if  (!cpu_has_mips_r6)

			break;

		*contpc = regs->cp0_epc + dec_insn.pc_inc +

			dec_insn.next_pc_inc;



		return 1;

#endif

	case cop0_op:

	case cop1_op: