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Commit 836ee0f7 authored by Stephen Boyd's avatar Stephen Boyd Committed by Michael Turquette
Browse files

clk: Convert __clk_get_name(hw->clk) to clk_hw_get_name(hw) 



Use the provider based method to get a clock's name so that we
can get rid of the clk member in struct clk_hw one day. Mostly
converted with the following coccinelle script.

@@
struct clk_hw *E;
@@

-__clk_get_name(E->clk)
+clk_hw_get_name(E)

Acked-by: default avatarHeiko Stuebner <heiko@sntech.de>
Cc: Sylwester Nawrocki <s.nawrocki@samsung.com>
Cc: Tomasz Figa <tomasz.figa@gmail.com>
Cc: Peter De Schrijver <pdeschrijver@nvidia.com>
Cc: Prashant Gaikwad <pgaikwad@nvidia.com>
Cc: Stephen Warren <swarren@wwwdotorg.org>
Acked-by: default avatarThierry Reding <treding@nvidia.com>
Cc: Thierry Reding <thierry.reding@gmail.com>
Cc: Alexandre Courbot <gnurou@gmail.com>
Cc: Tero Kristo <t-kristo@ti.com>
Cc: Ulf Hansson <ulf.hansson@linaro.org>
Acked-by: default avatarSebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Acked-by: default avatarAndrew Bresticker <abrestic@chromium.org>
Cc: Ezequiel Garcia <ezequiel.garcia@imgtec.com>
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: Kevin Cernekee <cernekee@chromium.org>
Acked-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
Cc: Ulrich Hecht <ulrich.hecht+renesas@gmail.com>
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-rockchip@lists.infradead.org
Cc: linux-samsung-soc@vger.kernel.org
Cc: linux-tegra@vger.kernel.org
Cc: linux-omap@vger.kernel.org
Signed-off-by: default avatarStephen Boyd <sboyd@codeaurora.org>
parent e7df6f6e

drivers/clk/berlin/berlin2-pll.c

+2 −2
Original line number Diff line number Diff line
@@ -61,7 +61,7 @@ berlin2_pll_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) 
	fbdiv = (val >> map->fbdiv_shift) & FBDIV_MASK;

	rfdiv = (val >> map->rfdiv_shift) & RFDIV_MASK;

	if (rfdiv == 0) {

		pr_warn("%s has zero rfdiv\n", __clk_get_name(hw->clk));

		pr_warn("%s has zero rfdiv\n", clk_hw_get_name(hw));

		rfdiv = 1;

	}
@@ -70,7 +70,7 @@ berlin2_pll_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) 
	vcodiv = map->vcodiv[vcodivsel];

	if (vcodiv == 0) {

		pr_warn("%s has zero vcodiv (index %d)\n",

			__clk_get_name(hw->clk), vcodivsel);

			clk_hw_get_name(hw), vcodivsel);

		vcodiv = 1;

	}

drivers/clk/clk-xgene.c

+11 −11
Original line number Diff line number Diff line
@@ -74,7 +74,7 @@ static int xgene_clk_pll_is_enabled(struct clk_hw *hw) 
	u32 data;



	data = xgene_clk_read(pllclk->reg + pllclk->pll_offset);

	pr_debug("%s pll %s\n", __clk_get_name(hw->clk),

	pr_debug("%s pll %s\n", clk_hw_get_name(hw),

		data & REGSPEC_RESET_F1_MASK ? "disabled" : "enabled");



	return data & REGSPEC_RESET_F1_MASK ? 0 : 1;
@@ -112,7 +112,7 @@ static unsigned long xgene_clk_pll_recalc_rate(struct clk_hw *hw, 
		fref = parent_rate / nref;

		fvco = fref * nfb;

	}

	pr_debug("%s pll recalc rate %ld parent %ld\n", __clk_get_name(hw->clk),

	pr_debug("%s pll recalc rate %ld parent %ld\n", clk_hw_get_name(hw),

		fvco / nout, parent_rate);



	return fvco / nout;
@@ -225,7 +225,7 @@ static int xgene_clk_enable(struct clk_hw *hw) 
		spin_lock_irqsave(pclk->lock, flags);



	if (pclk->param.csr_reg != NULL) {

		pr_debug("%s clock enabled\n", __clk_get_name(hw->clk));

		pr_debug("%s clock enabled\n", clk_hw_get_name(hw));

		reg = __pa(pclk->param.csr_reg);

		/* First enable the clock */

		data = xgene_clk_read(pclk->param.csr_reg +
@@ -234,7 +234,7 @@ static int xgene_clk_enable(struct clk_hw *hw) 
		xgene_clk_write(data, pclk->param.csr_reg +

					pclk->param.reg_clk_offset);

		pr_debug("%s clock PADDR base %pa clk offset 0x%08X mask 0x%08X value 0x%08X\n",

			__clk_get_name(hw->clk), &reg,

			clk_hw_get_name(hw), &reg,

			pclk->param.reg_clk_offset, pclk->param.reg_clk_mask,

			data);
@@ -245,7 +245,7 @@ static int xgene_clk_enable(struct clk_hw *hw) 
		xgene_clk_write(data, pclk->param.csr_reg +

					pclk->param.reg_csr_offset);

		pr_debug("%s CSR RESET PADDR base %pa csr offset 0x%08X mask 0x%08X value 0x%08X\n",

			__clk_get_name(hw->clk), &reg,

			clk_hw_get_name(hw), &reg,

			pclk->param.reg_csr_offset, pclk->param.reg_csr_mask,

			data);

	}
@@ -266,7 +266,7 @@ static void xgene_clk_disable(struct clk_hw *hw) 
		spin_lock_irqsave(pclk->lock, flags);



	if (pclk->param.csr_reg != NULL) {

		pr_debug("%s clock disabled\n", __clk_get_name(hw->clk));

		pr_debug("%s clock disabled\n", clk_hw_get_name(hw));

		/* First put the CSR in reset */

		data = xgene_clk_read(pclk->param.csr_reg +

					pclk->param.reg_csr_offset);
@@ -292,10 +292,10 @@ static int xgene_clk_is_enabled(struct clk_hw *hw) 
	u32 data = 0;



	if (pclk->param.csr_reg != NULL) {

		pr_debug("%s clock checking\n", __clk_get_name(hw->clk));

		pr_debug("%s clock checking\n", clk_hw_get_name(hw));

		data = xgene_clk_read(pclk->param.csr_reg +

					pclk->param.reg_clk_offset);

		pr_debug("%s clock is %s\n", __clk_get_name(hw->clk),

		pr_debug("%s clock is %s\n", clk_hw_get_name(hw),

			data & pclk->param.reg_clk_mask ? "enabled" :

							"disabled");

	}
@@ -318,13 +318,13 @@ static unsigned long xgene_clk_recalc_rate(struct clk_hw *hw, 
		data &= (1 << pclk->param.reg_divider_width) - 1;



		pr_debug("%s clock recalc rate %ld parent %ld\n",

			__clk_get_name(hw->clk),

			clk_hw_get_name(hw),

			parent_rate / data, parent_rate);



		return parent_rate / data;

	} else {

		pr_debug("%s clock recalc rate %ld parent %ld\n",

			__clk_get_name(hw->clk), parent_rate, parent_rate);

			clk_hw_get_name(hw), parent_rate, parent_rate);

		return parent_rate;

	}

}
@@ -356,7 +356,7 @@ static int xgene_clk_set_rate(struct clk_hw *hw, unsigned long rate, 
		data |= divider;

		xgene_clk_write(data, pclk->param.divider_reg +

					pclk->param.reg_divider_offset);

		pr_debug("%s clock set rate %ld\n", __clk_get_name(hw->clk),

		pr_debug("%s clock set rate %ld\n", clk_hw_get_name(hw),

			parent_rate / divider_save);

	} else {

		divider_save = 1;

drivers/clk/pistachio/clk-pll.c

+2 −2
Original line number Diff line number Diff line
@@ -174,7 +174,7 @@ static int pll_gf40lp_frac_set_rate(struct clk_hw *hw, unsigned long rate, 
	struct pistachio_pll_rate_table *params;

	int enabled = pll_gf40lp_frac_is_enabled(hw);

	u32 val, vco, old_postdiv1, old_postdiv2;

	const char *name = __clk_get_name(hw->clk);

	const char *name = clk_hw_get_name(hw);



	if (rate < MIN_OUTPUT_FRAC || rate > MAX_OUTPUT_FRAC)

		return -EINVAL;
@@ -316,7 +316,7 @@ static int pll_gf40lp_laint_set_rate(struct clk_hw *hw, unsigned long rate, 
	struct pistachio_pll_rate_table *params;

	int enabled = pll_gf40lp_laint_is_enabled(hw);

	u32 val, vco, old_postdiv1, old_postdiv2;

	const char *name = __clk_get_name(hw->clk);

	const char *name = clk_hw_get_name(hw);



	if (rate < MIN_OUTPUT_LA || rate > MAX_OUTPUT_LA)

		return -EINVAL;

drivers/clk/qcom/clk-branch.c

+1 −1
Original line number Diff line number Diff line
@@ -75,7 +75,7 @@ static int clk_branch_wait(const struct clk_branch *br, bool enabling, 
		bool (check_halt)(const struct clk_branch *, bool))

{

	bool voted = br->halt_check & BRANCH_VOTED;

	const char *name = __clk_get_name(br->clkr.hw.clk);

	const char *name = clk_hw_get_name(&br->clkr.hw);



	/* Skip checking halt bit if the clock is in hardware gated mode */

	if (clk_branch_in_hwcg_mode(br))

drivers/clk/rockchip/clk-inverter.c

+1 −1
Original line number Diff line number Diff line
@@ -50,7 +50,7 @@ static int rockchip_inv_set_phase(struct clk_hw *hw, int degrees) 
		val = !!degrees;

	} else {

		pr_err("%s: unsupported phase %d for %s\n",

		       __func__, degrees, __clk_get_name(hw->clk));

		       __func__, degrees, clk_hw_get_name(hw));

		return -EINVAL;

	}