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Commit 82fea5a1 authored by Vineet Gupta's avatar Vineet Gupta
Browse files

ARCv2: SMP: Support ARConnect (MCIP) for Inter-Core-Interrupts et al 



Cc: Jason Cooper <jason@lakedaemon.net>
Cc: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: default avatarVineet Gupta <vgupta@synopsys.com>
parent 173eaafa

arch/arc/Kconfig

+14 −7
Original line number Diff line number Diff line
@@ -160,12 +160,12 @@ config CPU_BIG_ENDIAN 
	  Build kernel for Big Endian Mode of ARC CPU



config SMP

	bool "Symmetric Multi-Processing (Incomplete)"

	bool "Symmetric Multi-Processing"

	default n

	select ARC_HAS_COH_CACHES if ISA_ARCV2

	select ARC_MCIP if ISA_ARCV2

	help

	  This enables support for systems with more than one CPU. If you have

	  a system with only one CPU, say N. If you have a system with more

	  than one CPU, say Y.

	  This enables support for systems with more than one CPU.



if SMP
@@ -175,13 +175,20 @@ config ARC_HAS_COH_CACHES 
config ARC_HAS_REENTRANT_IRQ_LV2

	def_bool n



endif	#SMP

config ARC_MCIP

	bool "ARConnect Multicore IP (MCIP) Support "

	depends on ISA_ARCV2

	help

	  This IP block enables SMP in ARC-HS38 cores.

	  It provides for cross-core interrupts, multi-core debug

	  hardware semaphores, shared memory,....



config NR_CPUS

	int "Maximum number of CPUs (2-4096)"

	range 2 4096

	depends on SMP

	default "2"

	default "4"



endif	#SMP



menuconfig ARC_CACHE

	bool "Enable Cache Support"

arch/arc/include/asm/irq.h

+1 −0
Original line number Diff line number Diff line
@@ -19,6 +19,7 @@ 
#else

#define TIMER0_IRQ      16

#define TIMER1_IRQ      17

#define IPI_IRQ         19

#endif



#include <linux/interrupt.h>

arch/arc/include/asm/mcip.h

0 → 100644
+91 −0
Original line number Diff line number Diff line 
/*

 * ARConnect IP Support (Multi core enabler: Cross core IPI, RTC ...)

 *

 * Copyright (C) 2014-15 Synopsys, Inc. (www.synopsys.com)

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 as

 * published by the Free Software Foundation.

 */



#ifndef __ASM_MCIP_H

#define __ASM_MCIP_H



#ifdef CONFIG_ISA_ARCV2



#include <asm/arcregs.h>



#define ARC_REG_MCIP_BCR	0x0d0

#define ARC_REG_MCIP_CMD	0x600

#define ARC_REG_MCIP_WDATA	0x601

#define ARC_REG_MCIP_READBACK	0x602



struct mcip_cmd {

#ifdef CONFIG_CPU_BIG_ENDIAN

	unsigned int pad:8, param:16, cmd:8;

#else

	unsigned int cmd:8, param:16, pad:8;

#endif



#define CMD_INTRPT_GENERATE_IRQ		0x01

#define CMD_INTRPT_GENERATE_ACK		0x02

#define CMD_INTRPT_READ_STATUS		0x03

#define CMD_INTRPT_CHECK_SOURCE		0x04



/* Semaphore Commands */

#define CMD_SEMA_CLAIM_AND_READ		0x11

#define CMD_SEMA_RELEASE		0x12



#define CMD_DEBUG_SET_MASK		0x34

#define CMD_DEBUG_SET_SELECT		0x36



#define CMD_IDU_ENABLE			0x71

#define CMD_IDU_DISABLE			0x72

#define CMD_IDU_SET_MODE		0x74

#define CMD_IDU_SET_DEST		0x76

#define CMD_IDU_SET_MASK		0x7C



#define IDU_M_TRIG_LEVEL		0x0

#define IDU_M_TRIG_EDGE			0x1



#define IDU_M_DISTRI_RR			0x0

#define IDU_M_DISTRI_DEST		0x2

};



/*

 * MCIP programming model

 *

 * - Simple commands write {cmd:8,param:16} to MCIP_CMD aux reg

 *   (param could be irq, common_irq, core_id ...)

 * - More involved commands setup MCIP_WDATA with cmd specific data

 *   before invoking the simple command

 */

static inline void __mcip_cmd(unsigned int cmd, unsigned int param)

{

	struct mcip_cmd buf;



	buf.pad = 0;

	buf.cmd = cmd;

	buf.param = param;



	WRITE_AUX(ARC_REG_MCIP_CMD, buf);

}



/*

 * Setup additional data for a cmd

 * Callers need to lock to ensure atomicity

 */

static inline void __mcip_cmd_data(unsigned int cmd, unsigned int param,

				   unsigned int data)

{

	write_aux_reg(ARC_REG_MCIP_WDATA, data);



	__mcip_cmd(cmd, param);

}



extern void mcip_init_early_smp(void);

extern void mcip_init_smp(unsigned int cpu);



#endif



#endif

arch/arc/kernel/Makefile

+1 −0
Original line number Diff line number Diff line
@@ -15,6 +15,7 @@ obj-$(CONFIG_ISA_ARCV2) += entry-arcv2.o intc-arcv2.o 


obj-$(CONFIG_MODULES)			+= arcksyms.o module.o

obj-$(CONFIG_SMP) 			+= smp.o

obj-$(CONFIG_ARC_MCIP)			+= mcip.o

obj-$(CONFIG_ARC_DW2_UNWIND)		+= unwind.o

obj-$(CONFIG_KPROBES)      		+= kprobes.o

obj-$(CONFIG_ARC_EMUL_UNALIGNED) 	+= unaligned.o

arch/arc/kernel/intc-arcv2.c

+1 −1
Original line number Diff line number Diff line
@@ -107,7 +107,7 @@ static struct irq_chip arcv2_irq_chip = { 
static int arcv2_irq_map(struct irq_domain *d, unsigned int irq,

			 irq_hw_number_t hw)

{

	if (irq == TIMER0_IRQ)

	if (irq == TIMER0_IRQ || irq == IPI_IRQ)

		irq_set_chip_and_handler(irq, &arcv2_irq_chip, handle_percpu_irq);

	else

		irq_set_chip_and_handler(irq, &arcv2_irq_chip, handle_level_irq);