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Commit 828fcfe3 authored by Zhou Wang's avatar Zhou Wang Committed by Wei Xu
Browse files

ARM: dts: hip04: add GPIO pieces 



Hisilicon Soc hip04 has four GPIO controllers, each one has 32
GPIOs and can be configured to be an interrupt controller.The GPIO
controllers are compatible with the snps,dw-apb-gpio driver.
This patch add the corresponding device tree nodes.

Acked-by: default avatarLinus Walleij <linus.walleij@linaro.org>
Signed-off-by: default avatarZhou Wang <wangzhou1@hisilicon.com>
Signed-off-by: default avatarWei Xu <xuwei5@hisilicon.com>
parent b787f68c

arch/arm/boot/dts/hip04.dtsi

+75 −0
Original line number Diff line number Diff line
@@ -269,6 +269,81 @@ 
			interrupts = <0 372 4>;

		};



		gpio@4003000 {

			#address-cells = <1>;

			#size-cells = <0>;

			compatible = "snps,dw-apb-gpio";

			reg = <0x4003000 0x1000>;



			gpio3: gpio-controller@0 {

				compatible = "snps,dw-apb-gpio-port";

				gpio-controller;

				#gpio-cells = <2>;

				snps,nr-gpios = <32>;

				reg = <0>;

				interrupt-parent = <&gic>;

				interrupt-controller;

				#interrupt-cells = <2>;

				interrupts = <0 392 4>;

			};

		};



		gpio@4002000 {

			#address-cells = <1>;

			#size-cells = <0>;

			compatible = "snps,dw-apb-gpio";

			reg = <0x4002000 0x1000>;



			gpio2: gpio-controller@0 {

			compatible = "snps,dw-apb-gpio-port";

				gpio-controller;

				#gpio-cells = <2>;

				snps,nr-gpios = <32>;

				reg = <0>;

				interrupt-parent = <&gic>;

				interrupt-controller;

				#interrupt-cells = <2>;

				interrupts = <0 391 4>;

			};

		};



		gpio@4001000 {

			#address-cells = <1>;

			#size-cells = <0>;

			compatible = "snps,dw-apb-gpio";

			reg = <0x4001000 0x1000>;



			gpio1: gpio-controller@0 {

				compatible = "snps,dw-apb-gpio-port";

				gpio-controller;

				#gpio-cells = <2>;

				snps,nr-gpios = <32>;

				reg = <0>;

				interrupt-parent = <&gic>;

				interrupt-controller;

				#interrupt-cells = <2>;

				interrupts = <0 390 4>;

			};

		};



		gpio@4000000 {

			#address-cells = <1>;

			#size-cells = <0>;

			compatible = "snps,dw-apb-gpio";

			reg = <0x4000000 0x1000>;



			gpio0: gpio-controller@0 {

				compatible = "snps,dw-apb-gpio-port";

				gpio-controller;

				#gpio-cells = <2>;

				snps,nr-gpios = <32>;

				reg = <0>;

				interrupt-parent = <&gic>;

				interrupt-controller;

				#interrupt-cells = <2>;

				interrupts = <0 389 4>;

			};

		};

	};



	etb@0,e3c42000 {