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Commit 8221d706 authored by Christian König's avatar Christian König Committed by Alex Deucher
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drm/amdgpu: partially revert "modify amdgpu_fence_wait_any() to amdgpu_fence_wait_multiple()" v2 



That isn't used any more.

v2: rebase

Signed-off-by: default avatarChristian König <christian.koenig@amd.com>
Reviewed-by: default avatarChunming Zhou <david1.zhou@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 09bfda10

drivers/gpu/drm/amd/amdgpu/amdgpu.h

+5 −6
Original line number Diff line number Diff line
@@ -440,10 +440,9 @@ int amdgpu_fence_wait_next(struct amdgpu_ring *ring); 
int amdgpu_fence_wait_empty(struct amdgpu_ring *ring);

unsigned amdgpu_fence_count_emitted(struct amdgpu_ring *ring);



signed long amdgpu_fence_wait_multiple(struct amdgpu_device *adev,

signed long amdgpu_fence_wait_any(struct amdgpu_device *adev,

				  struct fence **array,

				  uint32_t count,

				       bool wait_all,

				  bool intr,

				  signed long t);

struct amdgpu_fence *amdgpu_fence_ref(struct amdgpu_fence *fence);

drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c

+9 −35
Original line number Diff line number Diff line
@@ -851,22 +851,6 @@ static bool amdgpu_test_signaled_any(struct fence **fences, uint32_t count) 
	return false;

}



static bool amdgpu_test_signaled_all(struct fence **fences, uint32_t count)

{

	int idx;

	struct fence *fence;



	for (idx = 0; idx < count; ++idx) {

		fence = fences[idx];

		if (fence) {

			if (!test_bit(FENCE_FLAG_SIGNALED_BIT, &fence->flags))

				return false;

		}

	}



	return true;

}



struct amdgpu_wait_cb {

	struct fence_cb base;

	struct task_struct *task;
@@ -885,7 +869,7 @@ static signed long amdgpu_fence_default_wait(struct fence *f, bool intr, 
	struct amdgpu_fence *fence = to_amdgpu_fence(f);

	struct amdgpu_device *adev = fence->ring->adev;



	return amdgpu_fence_wait_multiple(adev, &f, 1, false, intr, t);

	return amdgpu_fence_wait_any(adev, &f, 1, intr, t);

}



/**
@@ -894,23 +878,18 @@ static signed long amdgpu_fence_default_wait(struct fence *f, bool intr, 
 * @adev:     amdgpu device

 * @array:    the fence array with amdgpu fence pointer

 * @count:    the number of the fence array

 * @wait_all: the flag of wait all(true) or wait any(false)

 * @intr:     when sleep, set the current task interruptable or not

 * @t:        timeout to wait

 *

 * If wait_all is true, it will return when all fences are signaled or timeout.

 * If wait_all is false, it will return when any fence is signaled or timeout.

 * It will return when any fence is signaled or timeout.

 */

signed long amdgpu_fence_wait_multiple(struct amdgpu_device *adev,

				       struct fence **array,

				       uint32_t count,

				       bool wait_all,

				       bool intr,

				       signed long t)

signed long amdgpu_fence_wait_any(struct amdgpu_device *adev,

				  struct fence **array, uint32_t count,

				  bool intr, signed long t)

{

	long idx = 0;

	struct amdgpu_wait_cb *cb;

	struct fence *fence;

	unsigned idx;



	BUG_ON(!array);
@@ -927,9 +906,6 @@ signed long amdgpu_fence_wait_multiple(struct amdgpu_device *adev, 
			if (fence_add_callback(fence,

					&cb[idx].base, amdgpu_fence_wait_cb)) {

				/* The fence is already signaled */

				if (wait_all)

					continue;

				else

				goto fence_rm_cb;

			}

		}
@@ -945,9 +921,7 @@ signed long amdgpu_fence_wait_multiple(struct amdgpu_device *adev, 
		 * amdgpu_test_signaled_any must be called after

		 * set_current_state to prevent a race with wake_up_process

		 */

		if (!wait_all && amdgpu_test_signaled_any(array, count))

			break;

		if (wait_all && amdgpu_test_signaled_all(array, count))

		if (amdgpu_test_signaled_any(array, count))

			break;



		if (adev->needs_reset) {

drivers/gpu/drm/amd/amdgpu/amdgpu_sa.c

+2 −2
Original line number Diff line number Diff line
@@ -367,8 +367,8 @@ int amdgpu_sa_bo_new(struct amdgpu_device *adev, 
		} while (amdgpu_sa_bo_next_hole(sa_manager, fences, tries));



		spin_unlock(&sa_manager->wq.lock);

		t = amdgpu_fence_wait_multiple(adev, fences, AMDGPU_MAX_RINGS, false, false,

						MAX_SCHEDULE_TIMEOUT);

		t = amdgpu_fence_wait_any(adev, fences, AMDGPU_MAX_RINGS,

					  false, MAX_SCHEDULE_TIMEOUT);

		r = (t > 0) ? 0 : t;

		spin_lock(&sa_manager->wq.lock);

		/* if we have nothing to wait for block */